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? freescale semiconductor, inc., 2004. all rights reserved. freescale semiconductor technical data this document contains detailed information about power considerations, dc/ac electrical characteristics, and ac timing specifications for .13m (hip7) members of the powerquicc ii? family of integrated communications processors?the mpc8280, the mpc8275, and the MPC8270 (collectively called 'the mpc8280' throughout this document ). mpc8280ec rev. 1.3, 01/2005 contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . 7 3. dc electrical characteristics . . . . . . . . . . . . . . . . . . . 8 4. thermal characteristics . . . . . . . . . . . . . . . . . . . . . . 11 5. power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6. ac electrical characteristics . . . . . . . . . . . . . . . . . . 14 7. clock configuration modes . . . . . . . . . . . . . . . . . . . 23 8. pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9. package description . . . . . . . . . . . . . . . . . . . . . . . . . 72 10. ordering information . . . . . . . . . . . . . . . . . . . . . . . . 74 11. document revision history . . . . . . . . . . . . . . . . . . . 75 mpc8280 powerquicc ii? family hardware specifications
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 2 freescale semiconductor overview 1overview table 1 shows the functionality supported by each device in the mpc8280 family. devices in the mpc8280 family are available in three packages?the standard zu package and the alternate vr or zq packages?as shown in table 2 . note that throughout this document references to the mpc8280 and the MPC8270 are inclusive of vr and zq package devices unless otherwise specified. for more information on vr and zq packages, contact your freescale sales office. for package ordering information, refer to section 10, ?ordering information .? table 1. mpc8280 powerquicc ii family functionality functionality devices MPC8270 mpc8275 mpc8280 package 1 1 refer to ta b l e 2 . 480 tbga 516 pbga 516 pbga 480 tbga serial communications controllers (sccs) 4 4 4 4 quicc multi-channel controller (qmc) ? ? ? ? fast communication controllers (fccs) 3 3 3 3 i-cache (kbyte) 16 16 16 16 d-cache (kbyte) 16 16 16 16 ethernet (10/100) 3 3 3 3 utopia ii ports 0 0 2 2 multi-channel controllers (mccs) 1 1 1 2 pci bridge yes yes yes yes transmission convergence (tc) layer ? ? ? yes inverse multiplexing for atm (ima) ? ? ? yes universal serial bus (usb) 2.0 full/low rate 1 1 1 1 security engine (sec) ? ? ? ? table 2. hip7 powerquicc ii device packages code (package) zu (480 tbga?leaded) vr (516 pbga?lead free) zq (516 pbga?lead spheres) device mpc8280 mpc8275vr mpc8275zq MPC8270 MPC8270vr MPC8270zq
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 3 overview figure 1 shows the block diagram. shaded portions are device-specific; refer to the notes below. figure 1. mpc8280 block diagram 1.1 features the major features of the mpc8280 are as follows: dual-issue integer (g2_le) core ? a core version of the ec603e microprocessor ? system core microprocessor supporting frequencies of 166?450 mhz ? separate 16-kbyte data and instruction caches: ? four-way set associative ? physically addressed ? lru replacement algorithm ? architecture-compliant memory management unit (mmu) 16 kbytes g2_le core i-cache i-mmu 16 kbytes d-cache d-mmu communication processor module (cpm) timers parallel i/o baud rate generators 32 kb 32-bit risc microcontroller and program rom serial dmas 4 virtual idmas 60x-to-pci bridge bridge memory controller clock counter system functions system interface unit (siu) local bus 32 bits, up to 100 mhz pci bus 32 bits, up to 66 mhz or mcc1 1 mcc2 fcc1 fcc2 fcc3 scc1 scc2 scc3 scc4/ smc1 smc2 spi i 2 c serial interface2 3 mii or rmii 2 utopia ports3 ports 60x bus microcode ima 1 data interrupt controller time slot assigner tc layer hardware1 8 tdm ports2 non-multiplexed i/o 60x-to-local bus interface unit 32 kb instruction notes: 1 mpc8280 only ( not on MPC8270, the vr package, nor the zq package) 2 mpc8280 has 2 serial interface (si) blocks and 8 tdm ports. MPC8270 and the vr and zq packages have only 1 si block and 4 tdm ports (tdm2[a?d]). 3 mpc8280, mpc8275vr, mpc8275zq only ( not on MPC8270, MPC8270vr, nor MPC8270zq) ram ram usb
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 4 freescale semiconductor overview ? common on-chip processor (cop) test interface ? high-performance (spec95 benchmark at 450 mhz; 855 dhrystones mips at 450 mhz) ? supports bus snooping for data cache coherency ? floating-point unit (fpu) separate power supply for internal logic and for i/o separate plls for g2_le core and for the cpm ? g2_le core and cpm can run at different frequencies for power/performance optimization ? internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 6:1, 7:1, 8:1 ratios ? internal cpm/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios 64-bit data and 32-bit address 60x bus ? bus supports multiple master designs ? supports single- and four-beat burst transfers ? 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller ? supports data parity or ecc and address parity 32-bit data and 18-bit address local bus ? single-master bus, supports external slaves ? eight-beat burst transfers ? 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller 60x-to-pci bridge ? programmable host bridge and agent ? 32-bit data bus, 66.67/83.3/100 mhz, 3.3 v ? synchronous and asynchronous 60x and pci clock modes ? all internal address space available to external pci host ? dma for memory block transfers ? pci-to-60x address remapping pci bridge ? pci specification revision 2.2 compliant and supports frequencies up to 66 mhz ? on-chip arbitration ? support for pci-to-60x-memory and 60x-memory-to-pci streaming ? pci host bridge or periphera l capabilities ? includes 4 dma channels for the following transfers: ? pci-to-60x to 60x-to-pci ? 60x-to-pci to pci-to-60x ? pci-to-60x to pci-to-60x ? 60x-to-pci to 60x-to-pci ? includes all of the configuration registers (which are automatically loaded from the eprom and used to configure the mpc8280) required by the pci standard as well as message and doorbell registers ? supports the i 2 o standard ? hot-swap friendly (supports the hot swap specification as defined by picmg 2.1 r1.0 august 3, 1998) ? support for 66.67/83.33/100 mhz, 3.3 v specification
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 5 overview ? 60x-pci bus core logic that uses a buffer pool to allocate buffers for each port ? uses the local bus signals, removing need for additional pins system interface unit (siu) ? clock synthesizer ? reset controller ? real-time clock (rtc) register ? periodic interrupt timer ? hardware bus monitor and software watchdog timer ? ieee 1149.1 jtag test access port 12-bank memory controller ? glueless interface to sram, page mode sdram, dram, eprom, flash and other user- definable peripherals ? byte write enables and selectable parity generation ? 32-bit address decodes with programmable bank size ? three user-programmable machines, general-purpose chip-select machine, and page-mode pipeline sdram machine ? byte selects for 64-bus width (60x) and byte selects for 32-bus width (local) ? dedicated interface logic for sdram cpu core can be disabled and the device can be used in slave mode to an external core communications processor module (cpm) ? embedded 32-bit communications processor (cp) uses a risc architecture for flexible support for communications protocols ? interfaces to g2_le core through an on-chip 32-kbyte dual-port data ram, an on-chip 32-kbyte dual-port instruction ram and dma controller ? serial dma channels for receive and transmit on all serial channels ? parallel i/o registers with open-drain and interrupt capability ? virtual dma functionality executing memory-to-memory and memory-to-i/o transfers ? three fast communications controllers supporting the following protocols: ? 10/100-mbit ethernet/ieee 802.3 cdma/cs interface through media independent interface (mii) or reduced media independent interface (rmii) ? atm?full-duplex sar protocols at 155 mbps, through utopia interface, aal5, aal1, aal0 protocols, tm 4.0 cbr, vbr, ubr, abr traffic types, up to 64 k external connections (no atm support for the MPC8270) ? transparent ? hdlc?up to t3 rates (clear channel) ? fcc2 can also be connected to the tc layer (mpc8280 only) ? two multichannel controllers (mccs) (one mcc on the MPC8270) ? each mcc handles 128 serial, full-duplex, 64-kbps data channels. each mcc can be split into four subgroups of 32 channels each. ? almost any combination of subgroups can be multiplexed to single or multiple tdm interfaces up to four tdm interfaces per mcc
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 6 freescale semiconductor overview ? four serial communications controllers (sccs) identical to those on the mpc860, supporting the digital portions of the following protocols: ? ethernet/ieee 802.3 cdma/cs ? hdlc/sdlc and hdlc bus ? universal asynchronous receiver transmitter (uart) ? synchronous uart ? binary synchronous (bisync) communications ? transparent ? universal serial bus (usb) controller ? supports usb 2.0 full/low rate compatible ? usb host mode ? supports control, bulk, interrupt, and isochronous data transfers ? crc16 generation and checking ? nrzi encoding/decoding with bit stuffing ? supports both 12- and 1.5-mbps data rates (automatic generation of preamble token and data rate configuration). note that low-speed operation requires an external hub. ? flexible data buffers with multiple buffers per frame ? supports local loopback mode for diagnostics (12 mbps only) ? supports usb slave mode ? four independent endpoints support control, bulk, interrupt, and isochronous data transfers ? crc16 generation and checking ? crc5 checking ? nrzi encoding/decoding with bit stuffing ? 12- or 1.5-mbps data rate ? flexible data buffers with multiple buffers per frame ? automatic retransmission upon transmit error ? two serial management controllers (smcs), identical to those of the mpc860 ? provide management for bri devices as general circuit interface (gci) controllers in time- division-multiplexed (tdm) channels ? transparent ? uart (low-speed operation) ? one serial peripheral interface identical to the mpc860 spi ? one inter-integrated circuit (i 2 c) controller (identical to the mpc860 i 2 c controller) ? microwire compatible ? multiple-master, single-master, and slave modes ? up to eight tdm interfaces (four on the MPC8270) ? supports two groups of four tdm channels for a total of eight tdms (one group of four on the MPC8270 and the mpc8275) ? 2,048 bytes of si ram ? bit or byte resolution ? independent transmit and receive routing, frame synchronization
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 7 operating conditions ? supports t1, cept, t1/e1, t3/e3, pulse code modulation highway, isdn basic rate, isdn primary rate, freescale interchip digital link (idl), general circuit interface (gci), and user-defined tdm serial interfaces ? eight independent baud rate generators and 20 input clock pins for supplying clocks to fccs, sccs, smcs, and serial channels ? four independent 16-bit timers that can be interconnected as two 32-bit timers inverse multiplexing for atm capabilities (ima) (mpc8280 only).supported by eight transfer transmission convergence (tc) layers between the tdms and fcc2. transmission convergence (tc) layer (mpc8280 only) 2 operating conditions table 3 shows the maximum electrical ratings. table 4 lists recommended operational voltage conditions. table 3. absolute maximum ratings 1 1 absolute maximum ratings are stress ratings only; functional operation (see ta b l e 4 ) at the maximums is not guaranteed. stress beyond those listed may affect device reliab ility or cause perm anent damage. rating symbol value unit core supply voltage 2 2 caution: vdd/vccsyn must not exceed vddh by more than 0.4 v during normal operation. it is recommended that vdd/vccsyn should be raised before or simultaneo us with vddh during power-on reset. vdd/vccsyn may exceed vddh by more than 0.4 v during power-on reset for no more than 100 ms. vdd -0.3 ? 2.25 v pll supply voltage 2 vccsyn -0.3 ? 2.25 v i/o supply voltage 3 3 caution: vddh can exceed vdd/vccsyn by 3.3 v during power on reset by no more than 100 msec. vddh should not exceed vdd/vccsyn by more than 2.5 v during normal operation. vddh -0.3 ? 4.0 v input voltage 4 4 caution: vin must not exceed vddh by more than 2.5 v at any time, including during power-on reset. vin gnd(-0.3) ? 3.6 v junction temperature t j 120 c storage temperature range t stg (-55) ? (+150) c table 4. recommended operating conditions 1 rating symbol value unit core supply voltage vdd 1.45 ? 1.60 v pll supply voltage vccsyn 1.45 ? 1.60 v i/o supply voltage vddh 3.135 ? 3.465 v input voltage vin gnd (-0.3) ? 3.465 v junction temperature (maximum) t j 105 2 c ambient temperature t a 0?70 2 c
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 8 freescale semiconductor dc electrical characteristics this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either gnd or v cc ). figure 2 shows the undershoot and overshoot voltage of the 60x and local bus memory interface of the mpc8280. note that in pci mode the i/o interface is different. figure 2. overshoot/undershoot voltage 3 dc electrical characteristics table 5 shows dc electrical characteristics. 1 caution: these are the recommended and tested operating conditions. proper operation outside of these conditions is not guaranteed. 2 note that for extended temperature parts the range is (-40) t a ? 105 t j . table 5. dc electrical characteristics 1 characteristic symbol min max unit input high voltage? all inputs except tck, trst and poreset 2 v ih 2.0 3.465 v input low voltage v il gnd 0.8 v clkin input high voltage v ihc 2.4 3.465 v clkin input low voltage v ilc gnd 0.4 v input leakage current, v in = vddh 3 i in ?10a hi-z (off state) leakage current, v in = vddh 3 i oz ?10a signal low input current, v il = 0.8 v 4 i l ?1a signal high input current, v ih = 2.0 v i h ?1a gnd gnd ? 0.3 v gnd ? 1.0 v not to exceed 10% gv dd of t sdram_clk gv dd + 5% 4 v v ih v il
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 9 dc electrical characteristics output high voltage, i oh = ?2 ma except utopia mode, and open drain pins in utopia mode 5 (utopia pins only): i oh = -8.0ma pa[0-31] pb[4-31] pc[0-31] pd[4-31] v oh 2.4 ? v in utopia mode 5 (utopia pins only): i ol = 8.0ma pa [0 - 31 ] pb[4-31] pc[0-31] pd[4-31] v ol ?0.5 v i ol = 6.0ma br bg abb/irq2 ts a[0-31] tt[0-4] tbst tsize[0?3] aack artry dbg dbb /irq3 d[0-63] dp(0)/rsrv /ext_br2 dp(1)/irq1 /ext_bg2 dp(2)/tlbisync /irq2 /ext_dbg2 dp(3)/irq3 /ext_br3 /ckstp_out dp(4)/irq4 /ext_bg3 /core_srest dp(5)/tben/ext_dbg3 /irq5 /cint dp(6)/cse(0)/irq6 dp(7)/cse(1)/irq7 psdval ta tea gbl /irq1 ci/ baddr29/irq2 wt /baddr30/irq3 l2_hit /irq4 cpu_bg/ baddr31/irq5 /cint cpu_dbg cpu_br irq0 /nmi_out irq7 /int_out /ape poreset hreset sreset rstconf v ol ?0.4 v table 5. dc electrical characteristics 1 (continued) characteristic symbol min max unit
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 10 freescale semiconductor dc electrical characteristics i ol = 5.3ma cs [0-9] cs (10)/bctl1 cs (11)/ap(0) baddr[27?28] ale bctl0 pwe [0?7]/psddqm [0?7]/pbs [0?7] psda10/pgpl0 psdwe/ pgpl1 poe /psdras /pgpl2 psdcas/pgpl3 pgta/pupmwait/pgpl4/ppbs psdamux/pgpl5 lwe [0?3]lsddqm [0?3]/lbs [0?3]/pci_cfg[0?3] lsda10/lgpl0/pci_modckh0 lsdwe/lgpl1/pci_modckh1 loe /lsdras /lgpl2/pci_modckh2 lsdcas/lgpl3/pci_modckh3 lgta/lupmwait/lgpl4/lpbs lsdamux/lgpl5/pci_modck lwr modck[1?3]/ap[1?3]/tc[0?2]/bnksel[0?2] i ol = 3.2ma l_a14/par l_a15/frame /smi l_a16/trdy l_a17/irdy /ckstp_out l_a18/stop l_a19/devsel l_a20/idsel l_a21/perr l_a22/serr l_a23/req0 l_a24/req1/hsejsw l_a25/gnt0 l_a26/gnt1/hsled l_a27/gnt2/hsenum l_a28/rst /core_sreset l_a29/inta l_a30/req2 l_a31 lcl_d[0-31]/ad[0-31] lcl_dp[0-3]/c/be [0-3] pa[0?31] pb[4?31] pc[0?31] pd[4?31] tdo qreq v ol ?0.4 v 1 the default configuration of the cpm pins (pa[0?31], pb[4?31], pc[0?31], pd[4?31]) is input. to prevent excessive dc current, it is recommended to either pull unused pins to gnd or vddh, or to configure them as outputs. 2 tck, trst and poreset have min vih = 2.5v table 5. dc electrical characteristics 1 (continued) characteristic symbol min max unit
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 11 thermal characteristics 4 thermal characteristics table 6 describes thermal characteristics for both the packages. see table 2 for information about a given device?s package. for the discussions sections 4.1 and 4.5, p d = (v dd i dd ) + pi/o, where pi/o is the power dissipation of the i/o drivers. 4.1 estimation with junction-to-ambient thermal resistance an estimation of the chip junction temperature, t j , in c can be obtained from the following equation: t j = t a + (r ja p d ) where: t a = ambient temperature (oc) r ja = package junction-to-ambient thermal resistance (oc/w) p d = power dissipation in package the junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. however, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity t j ? t a ) are possible. 3 the leakage current is measured for nominal vddh,vccsyn, and vdd. 4 v il for iic interface does not match iic standard, but does meet iic standard for v ol and should not cause any compatibility issue 5 mpc8280, mpc8275vr, mpc8275zq only table 6. thermal characteristics characteristic symbol value unit air flow 480 tbga 516 pbga junction to ambient? single-layer board 1 1 assumes no thermal vias r ja 16 27 c/w natural convection 11 21 1 m/s junction to ambient? four-layer board r ja 12 19 c/w natural convection 916 1 m/s junction to board 2 2 thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. r jb 611 c/w ? junction to case 3 3 thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). r jc 28 c/w ? junction-to-package top 4 4 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. jt 22 c/w ?
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 12 freescale semiconductor thermal characteristics 4.2 estimation with junction-to-case thermal resistance historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: r ja = r jc + r ca where: r ja = junction-to-ambient thermal resistance (oc/w) r jc = junction-to-case thermal resistance (oc/w) r ca = case-to-ambient thermal resistance (oc/w) r jc is device related and cannot be influenced by the user. the user adjusts the thermal environment to affect the case-to-ambient thermal resistance, r ca . for instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. this thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink to the ambient environment. for most packages, a better model is required. 4.3 estimation with junction-to-board thermal resistance a simple package thermal model which has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. the junction-to-case thermal resistance covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. the junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. it has been observed that the thermal performance of most plastic packages, especially pbga packages, is strongly dependent on the board temperature. if the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: t j = t b + (r jb p d ) where: r jb = junction-to-board thermal resistance (oc/w) t b = board temperature (oc) p d = power dissipation in package if the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. for this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and by attaching the thermal balls to the ground plane. 4.4 estimation using simulation when the board temperature is not known, a thermal simulation of the application is needed. the simple two-resistor model can be used with the thermal simulation of the application, or a more accurate and complex model of the package can be used in the thermal simulation.
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 13 power dissipation 4.5 experimental determination to determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( jt p d ) where: jt = thermal characterization parameter t t = thermocouple temperature on top of package p d = power dissipation in package the thermal characterization parameter is measured per jedec jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the case to avoid measurement errors caused by cooling effects of the thermocouple wire. 4.6 layout practices each vdd and vddh pin should be provided with a low-impedance path to the board?s power supplies. each ground pin should likewise be provided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on chip. the vdd and vddh power supplies should be bypassed to ground using by-pass capacitors located as close as possible to the four sides of the package. for filtering high frequency noise, a capacitor of 0.1uf on each vdd and vddh pin is recommended. further, for medium frequency noise, a total of 2 capacitors of 47uf for vdd and 2 capacitors of 47uf for vddh are also recommnded. the capacitor leads and associated printed circuit traces connecting to chip vdd, vddh and ground should be kept to less than half an inch per capacitor lead. boards should employ separate inner layers for power and gnd planes. all output pins on the mpc8280 have fast rise and fall times. printed circuit (pc) trace interconnection length should be minimized to minimize overdamped conditions and reflections caused by these fast output switching times. this recommendation particularly applies to the address and data buses. maximum pc trace lengths of six inches are recommended. capacitance calculations should consider all device loads as well as parasitic capacitances due to the pc traces. attention to proper pcb layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the vdd and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. special care should be taken to minimize the noise levels on the pll supply pins. 5 power dissipation table 7 provides preliminary, estimated power dissipation for various configurations. note that suitable thermal management is required to ensure the junction temperature does not exceed the maximum specified value. also note that the i/o power should be included when determining whether to use a heat sink. for a complete list of possible clock configurations, refer to section 7, ?clock configuration modes .?
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 14 freescale semiconductor ac electrical characteristics 6 ac electrical characteristics the following sections include illustrations and tables of clock diagrams, signals, and cpm outputs and inputs for 66.67/83.33/100 mhz devices. note that ac timings are based on a 50-p f load. a derating factor of 0.5 ns per 10 p f may be applied. typical output buffer impedances are shown in table 8 . table 7. estimated power dissipation for various configurations 1 1 test temperature = 105 c bus (mhz) cpm multiplication factor cpm (mhz) cpu multiplication factor cpu (mhz) p int (w) 2, 3 2 p int = i dd x v dd watts 3 values do not include i/o. add the following estimates for active i/o based on the following bus speeds: 66.7 mhz = 0.45 w (nominal), 0.5 w (maximum) 83.3 mhz = 0.5w (nominal), 0.6 w (maximum) 100 mhz = 0.6 w (nominal), 0.7 w (maximum) vddl 1.5 volts nominal maximum 66.67 2.5 166 3.5 233 0.95 1.0 66.67 2.5 166 4 266 1.0 1.05 66.67 3 200 4 266 1.05 1.1 66.67 3.5 233 4.5 300 1.05 1.15 83.33 3 250 4 333 1.25 1.35 83.33 3 250 4.5 375 1.3 1.4 83.33 3.5 292 5 417 1.45 1.55 100 3 300 4 400 1.5 1.6 100 3 300 4.5 450 1.55 1.65 table 8. output buffer impedances 1 1 these are typical values at 65 c. impedance may vary by 25% with process and temperature. output buffers typical impedance ( ? ) 60x bus 45 or 27 2 2 on silicon revision 0.0 (mask #: 0k49m), selectable impedance is not available. impedance is set at 45 ? . on all other revisions, impedance value is selected through the siumcr[20,21]. refer to the mpc8280 powerquicc ii family reference manual . local bus 45 memory controller 45 or 27 2 parallel i/o 45 pci 27
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 15 ac electrical characteristics 6.1 cpm ac characteristics table 9 lists cpm output characteristics. table 10 lists cpm input characteristics. note: rise/fall time on cpm input pins it is recommended that the rise/fall time on cpm input pins should not exceed 5 ns. this should be enforced especially on clock signals. rise time refers to signal transitions from 10% to 90% of vcc; fall time refers to transitions from 90% to 10% of vcc. table 9. ac characteristics for cpm outputs 1 1 output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. spec number characteristic value (ns) max min maximum delay minimum delay 66 mhz 83 mhz 100 mhz 66 mhz 83 mhz 100 mhz sp36a sp37a fcc outputs?internal clock (nmsi) 6 5.5 5.5 0.5 0.5 0.5 sp36bsp37bfcc outputs?external clock (nmsi)888222 sp38a sp39a scc/smc/spi/i2c outputs?internal clock (nmsi) 10 10 10 0 0 0 sp38b sp39b scc/smc/spi/i2c outputs?external clock (nmsi) 888222 sp40 sp41 tdm outputs/si 11 11 11 2.5 2.5 2.5 sp42 sp43 timer/idma outputs 11 11 11 0.5 0.5 0.5 sp42a sp43a pio outputs 11 11 11 0.5 0.5 0.5 table 10. ac characteristics for cpm inputs 1 1 input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. spec number characteristic value (ns) setup hold setup hold 66 mhz 83 mhz 100 mhz 66 mhz 83 mhz 100 mhz sp16asp17afcc inputs?internal clock (nmsi)666000 sp16b sp17b fcc inputs?external clock (nmsi) 2.5 2.5 2.5 2 2 2 sp18a sp19a scc/smc/spi/i2c inputs?internal clock (nmsi) 666000 sp18b sp19b scc/smc/spi/i2c inputs?external clock (nmsi) 444222 sp20 sp21 tdm inputs/si 5 5 5 2.5 2.5 2.5 sp22 sp23 pio/timer/idma inputs 8 8 8 0.5 0.5 0.5
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 16 freescale semiconductor ac electrical characteristics note although the specifications generally reference the rising edge of the clock, the following ac timing diagrams also apply when the falling edge is the active edge. figure 3 shows the fcc internal clock. figure 3. fcc internal clock diagram figure 4 shows the fcc external clock. figure 4. fcc external clock diagram brg_out fcc input signals fcc output signals fcc output signals note: when gfmr.[tci] = 1 note: when gfmr[tci] = 0 sp36a/sp37a sp36a/sp37a sp17a sp16a serial clkin fcc input signals fcc output signals fcc output signals note: when gfmr[tci] = 1 note: when gfmr[tci] = 0 sp16b sp17b sp36b/sp37b sp36b/sp37b
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 17 ac electrical characteristics figure 5 shows the scc/smc/spi/i 2 c external clock. figure 5. scc/smc/spi/i 2 c external clock diagram figure 6 shows the scc/smc/spi/i 2 c internal clock. figure 6. scc/smc/spi/i 2 c internal clock diagram serial clkin scc/smc/spi/i2c input signals scc/smc/spi/i2c output signals sp18b sp19b sp38b/sp39b (see note) (see note) note: there are four possible timing conditions for scc and spi: 1. input sampled on the rising edge and output driven on the rising edge (shown). 2. input sampled on the rising edge and output driven on the falling edge. 3. input sampled on the falling edge and output driven on the falling edge. 4. input sampled on the falling edge and output driven on the rising edge. brg_out scc/smc/spi/i2c input signals scc/smc/spi/i2c output signals sp18a sp19a sp38a/sp39a (see note) (see note) note: there are four possible timing conditions for scc and spi: 1. input sampled on the rising edge and output driven on the rising edge (shown). 2. input sampled on the rising edge and output driven on the falling edge. 3. input sampled on the falling edge and output driven on the falling edge. 4. input sampled on the falling edge and output driven on the rising edge.
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 18 freescale semiconductor ac electrical characteristics figure 7 shows tdm input and output signals. figure 7. tdm signal diagram figure 8 shows pio and timer signals. figure 8. pio and timer signal diagram serial clkin tdm input signals tdm output signals sp20 sp21 sp40/sp41 note: there are four possible tdm timing conditions: 1. input sampled on the rising edge and output driven on the rising edge (shown). 2. input sampled on the rising edge and output driven on the falling edge. 3. input sampled on the falling edge and output driven on the falling edge. 4. input sampled on the falling edge and output driven on the rising edge. sys clk pio/idma/timer[tgate assertion] input signals idma output signals sp22 sp23 sp42/sp43 timer(sp42/43)/ pio(sp42a/sp43a) sp42a/sp43a output signals sp42/sp43 timer input signal [tgate deassertion] sp22 sp23 note: tgate is asserted on the rising edge of the clock; it is deasserted on the falling edge. (see note) (see note)
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 19 ac electrical characteristics 6.2 siu ac characteristics note: clkin jitter and duty cycle the clkin input to the mpc8280 should not exceed +/? 150 psec. this represents total input jitter?the combination of short term (peak-to-peak) and long term (cumulative). the duty cycle of clkin should not exceed the ratio of 40:60. note: spread spectrum clocking spread spectrum clocking is allowed with 1% input frequency down-spread at maximum 60 khz modulation rate regardless of input frequency. note: pci ac timing the mpc8280 meets the timing requirements of pci specification revision 2.2 . refer to sections 7.2 and 7.3 and ?note: tval (output hold)? to determine if a specific clock configuration is compliant. table 11 lists siu input characteristics. table 11. ac characteristics for siu inputs 1 1 input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. spec number characteristic value (ns) setup hold setup hold 66 mhz 83 mhz 100 mhz 66 mhz 83 mhz 100 mhz sp11 sp10 aack /ta /ts /dbg /bg /br /artry / tea 6 5 3.50.50.50.5 sp12 sp10 data bus in normal mode 5 4 3.5 0.5 0.5 0.5 sp13 sp10 data bus in ecc and parity modes 7 5 3.5 0.5 0.5 0.5 sp13a sp10 pipeline mode? data bus in ecc and parity modes 5 4 2.50.50.50.5 sp14 sp10 dp pins 7 5 3.5 0.5 0.5 0.5 sp14a sp10 pipeline mode?dp pins ? 4 2.5 ? 0.5 0.5 sp15 sp10 all other pins 5 4 3.5 0.5 0.5 0.5
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 20 freescale semiconductor ac electrical characteristics table 12 lists siu output characteristics. note activating data pipelining (setting br x [dr] in the memory controller) improves the ac timing. table 12. ac characteristics for siu outputs 1 1 output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. spec number characteristic value (ns) max min maximum delay minimum delay 66 mhz 83 mhz 100 mhz 66 mhz 83 mhz 100 mhz sp31 sp30 psdval /tea /ta 765.5111 sp32 sp30 add/add_atr./baddr/ci/gbl/wt 8 6.5 5.5 1 1 1 sp33a sp30 data bus 6.5 6.5 5.5 0.7 0.7 0.7 sp33b sp30 dp 6 5.5 5.5 1 1 1 sp34 sp30 memory controller signals/ale 6 5.5 5.5 1 1 1 sp35 sp30 all other signals 6 5.5 5.5 1 1 1 sp35asp30ap 777111
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 21 ac electrical characteristics figure 9 shows the interaction of several bus signals. figure 9. bus signals clkin aack /ta /ts / data bus normal mode all other input signals psdval /tea /ta output signals add/add_atr/baddr/ci/ data bus output signals all other output signals sp11 sp12 sp15 sp10 sp10 sp10 sp30 sp30 sp30 sp30 sp32 sp33a sp35 dbg /bg /br input signals gbl/wt output signals sp31 input signal ap signals sp30 sp35a artry /tea input signals sp11a sp10 (except ap)
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 22 freescale semiconductor ac electrical characteristics figure 10 shows signal behavior for all parity modes (including ecc, rmw parity, and standard parity). figure 10. parity mode diagram figure 11 shows signal behavior in memc mode. figure 11. memc mode diagram note generally, all mpc8280 bus and system output signals are driven from the rising edge of the input clock (clkin). memory controller signals, however, trigger on four points within a clkin cycle. each cycle is divided by four internal ticks: t1, t2, t3, and t4. t1 always occurs at the rising edge, and t3 at the falling edge, of clkin. however, the spacing of t2 and t4 depends on the pll clock ratio selected, as shown in ta ble 13 . clkin data bus, ecc, and parity mode pipeline mode? dp mode output signal sp13 sp10 sp14a sp10 pipeline mode? sp10 dp mode input signal sp14 sp10 data bus, ecc, and parity mode dp mode input signal input signals input signals sp30 sp33b sp13a clkin v_clk memory controller signals sp34/sp30
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 23 clock configuration modes figure 12 is a representation of the information in table 13 . figure 12. internal tick spacing for memory controller signals note the upm machine outputs change on the internal tick determined by the memory controller programming; the ac specifications are relative to the internal tick. note that sdram and gpcm machine outputs change on clkin?s rising edge. 7 clock configuration modes the mpc8280 has three clocking modes: local, pci host, and pci agent. the clocking mode is set according to three input pins?pci_mode, pci_cfg[0], pci_modck?as shown in ta ble 14 . table 13. tick spacing for memory controller signals pll clock ratio tick spacing (t1 occurs at the rising edge of clkin) t2 t3 t4 1:2, 1:3, 1:4, 1:5, 1:6 1/4 clkin 1/2 clkin 3/4 clkin 1:2.5 3/10 clkin 1/2 clkin 8/10 clkin 1:3.5 4/14 clkin 1/2 clkin 11/14 clkin table 14. mpc8280 clocking modes pins clocking mode pci clock frequency range (mhz) reference pci_mode pci_cfg[0] pci_modck 1 1 determines pci clock frequency range. refer to sections 7.2 and 7.3. 1 ? ? local bus ? table 15 0 0 0 pci host 50?66 ta ble 1 6 0 0 1 25?50 ta ble 1 7 0 1 0 pci agent 50?66 ta ble 1 8 0 1 1 25?50 ta ble 1 9 clkin t1 t2 t3 t4 clkin t1 t2 t3 t4 for 1:2.5 for 1:3.5 clkin t1 t2 t3 t4 for 1:2, 1:3, 1:4, 1:5, 1:6
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 24 freescale semiconductor clock configuration modes in each clocking mode, the configuration of bus, core, pci, and cpm frequencies is determined by seven bits during the power-up reset?three hardware configuration pins (modck[1?3]) and four bits from hardware configuration word[28?31] (modck_h). both the plls and the dividers are set according to the selected mpc8280 clock operation mode as described in the following sections. 7.1 local bus mode table 15 lists clock configurations for the mpc8280 in local bus mode. the frequencies listed are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user?s device. note clock configurations change only after poreset is asserted. table 15. clock configurations for local bus mode 1 mode 2 bus clock 3 (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) modck_h-modck[1-3] low high low high low high default modes (modck_h= 0000) 0000_000 37.5 133.3 3 112.5 400.0 4 150.0 533.3 0000_001 33.3 133.3 3 100.0 400.0 5 166.7 666.7 0000_010 37.5 100.0 4 150.0 400.0 4 150.0 400.0 0000_011 30.0 100.0 4 120.0 400.0 5 150.0 500.0 0000_100 60.0 167.0 2 120.0 334.0 2.5 150.0 417.5 0000_101 50.0 167.0 2 100.0 334.0 3 150.0 501.0 0000_110 60.0 160.0 2.5 150.0 400.0 2.5 150.0 400.0 0000_111 50.0 160.0 2.5 125.0 400.0 3 150.0 480.0 full configuration modes 0001_000 50.0 167.0 2 100.0 334.0 4 200.0 668.0 0001_001 50.0 167.0 2 100.0 334.0 5 250.0 835.0 0001_010 50.0 145.8 2 100.0 291.7 6 300.0 875.0 0001_011 reserved 0001_100 reserved 0001_101 37.5 133.3 3 112.5 400.0 4 150.0 533.3 0001_110 33.3 133.3 3 100.0 400.0 5 166.7 666.7 1000_111 33.3 133.3 3 100.0 400.0 5.5 183.3 733.3 0001_111 33.3 133.3 3 100.0 400.0 6 200.0 800.0 0010_000 reserved 0010_001 reserved
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 25 clock configuration modes 0010_010 37.5 100.0 4 150.0 400.0 4 150.0 400.0 0010_011 30.0 100.0 4 120.0 400.0 5 150.0 500.0 0010_100 25.0 100.0 4 100.0 400.0 6 150.0 600.0 0010_101 25.0 100.0 4 100.0 400.0 7 175.0 700.0 0010_110 25.0 100.0 4 100.0 400.0 8 200.0 800.0 0010_111 reserved 0011_000 30.0 80.0 5 150.0 400.0 5 150.0 400.0 0011_001 25.0 80.0 5 125.0 400.0 6 150.0 480.0 0011_010 25.0 80.0 5 125.0 400.0 7 175.0 560.0 0011_011 25.0 80.0 5 125.0 400.0 8 200.0 640.0 0011_100 reserved 0011_101 reserved 0011_110 25.0 66.7 6 150.0 400.0 6 150.0 400.0 0011_111 25.0 66.7 6 150.0 400.0 7 175.0 466.7 0100_000 25.0 66.7 6 150.0 400.0 8 200.0 533.3 0101_101 75.0 167.0 2 150.0 334.0 2 166.7 334.0 0101_110 60.0 167.0 2 120.0 334.0 2.5 166.7 417.5 0101_111 50.0 167.0 2 100.0 334.0 3 200.0 501.0 0110_000 50.0 167.0 2 100.0 334.0 3.5 250.0 584.5 0110_001 50.0 167.0 2 100.0 334.0 4 250.0 668.0 0110_010 50.0 167.0 2 100.0 334.0 4.5 250.0 751.5 0110_011 reserved 0110_100 60.0 160.0 2.5 150.0 400.0 2.5 150.0 400.0 0110_101 50.0 160.0 2.5 125.0 400.0 3 150.0 480.0 0110_110 42.9 160.0 2.5 107.1 400.0 3.5 150.0 560.0 0110_111 40.0 160.0 2.5 100.0 400.0 4 160.0 640.0 0111_000 40.0 160.0 2.5 100.0 400.0 4.5 180.0 720.0 table 15. clock configurations for local bus mode 1 (continued) mode 2 bus clock 3 (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) modck_h-modck[1-3] low high low high low high
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 26 freescale semiconductor clock configuration modes 0111_001 reserved 0111_010 reserved 0111_011 50.0 133.3 3 150.0 400.0 3 150.0 400.0 0111_100 42.9 133.3 3 128.6 400.0 3.5 150.0 466.7 0111_101 37.5 133.3 3 112.5 400.0 4 150.0 533.3 0111_110 33.3 133.3 3 100.0 400.0 4.5 150.0 600.0 0111_111 reserved 1000_000 reserved 1000_001 reserved 1000_010 42.9 114.3 3.5 150.0 400.0 3.5 150.0 400.0 1000_011 37.5 114.3 3.5 131.3 400.0 4 150.0 457.1 1000_100 33.3 114.3 3.5 116.7 400.0 4.5 150.0 514.3 1000_101 30.0 114.3 3.5 105.0 400.0 5 150.0 571.4 1000_110 28.6 114.3 3.5 100.0 400.0 5.5 150.0 628.6 1100_000 reserved 1100_001 reserved 1100_010 reserved 1101_000 reserved 1 the ?low? values are the minimum allowable frequencies for a given clock mode. the minimum bus frequency in a table entry guarantees only the required minimum cpu operating frequency. the ?high? values are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configuration does not violate the frequency rating of the user?s device. the minimum cpm frequency is 120 mhz. minimum cpu frequency is determined by the clock mode. for modes with a cpu multiplication factor <= 3, the minimum cpu frequency is 150 mhz for commercial temperature devices and 175 mhz for extended temperature devices. for modes with a cpu multiplication factor >= 3.5: for rev0.1 the minimum cpu frequency is 250 mhz; for reva or later the minimum cpu frequency is 150 mhz for commercial temperature devices and 175 mhz for extended temperature devices. 2 modck_h = hard reset configuration word [28?31]. modck[1-3] = three hardware configuration pins. 3 60x and local bus frequency. identical to clkin. 4 cpm multiplication factor = cpm clock/bus clock 5 cpu multiplication factor = core pll multiplication factor table 15. clock configurations for local bus mode 1 (continued) mode 2 bus clock 3 (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) modck_h-modck[1-3] low high low high low high
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 27 clock configuration modes 7.2 pci host mode table 16 and table 17 show clock configurations for pci host mode. the frequencies listed are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user?s device. in addition, note the following: note: pci_modck in pci mode only, pci_modck comes from the lgpl5 pin and modck_h[0?3] comes from {lgpl0, lgpl1, lgpl2, lgpl3}. note: tval (output hold) the minimum tval = 2 ns when pci_modck = 1, and the minimum tval = 1 ns when pci_modck = 0. therefore, designers should use clock configurations that fit this condition to achieve pci-compliant ac timing. table 16. clock configurations for pci host mode (pci_modck=0) 1, 2 mode 3 bus clock 4 (mhz) cpm multiplication factor 5 cpm clock (mhz) cpu multiplication factor 6 cpu clock (mhz) pci division factor pci clock (mhz) modck_h- modck[1-3] low high low high low high low high default modes (modck_h=0000) 0000_000 60.0 66.7 2 120.0 133.3 2.5 150.0 166.7 2 60.0 66.7 0000_001 50.0 66.7 2 100.0 133.3 3 150.0 200.0 2 50.0 66.7 0000_010 60.0 80.0 2.5 150.0 200.0 3 180.0 240.0 3 50.0 66.7 0000_011 60.0 80.0 2.5 150.0 200.0 3.5 210.0 280.0 3 50.0 66.7 0000_100 60.0 80.0 2.5 150.0 200.0 4 240.0 320.0 3 50.0 66.7 0000_101 50.0 66.7 3 150.0 200.0 3 150.0 200.0 3 50.0 66.7 0000_110 50.0 66.7 3.5 150.0 200.0 3.5 175.0 233.3 3 50.0 66.7 0000_111 50.0 66.7 3 150.0 200.0 4 200.0 266.6 3 50.0 66.7 full configuration modes 0001_000 50.0 66.7 3 150.0 200.0 5 250.0 333.3 3 50.0 66.7 0001_001 50.0 66.7 3 150.0 200.0 6 300.0 400.0 3 50.0 66.7 0001_010 50.0 66.7 3 150.0 200.0 7 350.0 466.6 3 50.0 66.7 0001_011 50.0 66.7 3 150.0 200.0 8 400.0 533.3 3 50.0 66.7 0010_000 50.0 66.7 4 200.0 266.6 5 250.0 333.3 4 50.0 66.7 0010_001 50.0 66.7 4 200.0 266.6 6 300.0 400.0 4 50.0 66.7 0010_010 50.0 66.7 4 200.0 266.6 7 350.0 466.6 4 50.0 66.7 0010_011 50.0 66.7 4 200.0 266.6 8 400.0 533.3 4 50.0 66.7
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 28 freescale semiconductor clock configuration modes 0010_100 75.0 100.0 4 300.0 400.0 5 375.0 500.0 6 50.0 66.7 0010_101 75.0 100.0 4 300.0 400.0 5.5 412.5 549.9 6 50.0 66.7 0010_110 75.0 100.0 4 300.0 400.0 6 450.0 599.9 6 50.0 66.7 0011_000 50.0 66.7 5 250.0 333.3 5 250.0 333.3 5 50.0 66.7 0011_001 50.0 66.7 5 250.0 333.3 6 300.0 400.0 5 50.0 66.7 0011_010 50.0 66.7 5 250.0 333.3 7 350.0 466.6 5 50.0 66.7 0011_011 50.0 66.7 5 250.0 333.3 8 400.0 533.3 5 50.0 66.7 0100_000 reserved 0100_001 50.0 66.7 6 300.0 400.0 6 300.0 400.0 6 50.0 66.7 0100_010 50.0 66.7 6 300.0 400.0 7 350.0 466.6 6 50.0 66.7 0100_011 50.0 66.7 6 300.0 400.0 8 400.0 533.3 6 50.0 66.7 0101_000 60.0 66.7 2 120.0 133.3 2.5 150.0 166.7 2 60.0 66.7 0101_001 50.0 66.7 2 100.0 133.3 3 150.0 200.0 2 50.0 66.7 0101_010 50.0 66.7 2 100.0 133.3 3.5 175.0 233.3 2 50.0 66.7 0101_011 50.0 66.7 2 100.0 133.3 4 200.0 266.6 2 50.0 66.7 0101_100 50.0 66.7 2 100.0 133.3 4.5 225.0 300.0 2 50.0 66.7 0110_000 60.0 80.0 2.5 150.0 200.0 2.5 150.0 200.0 3 50.0 66.7 0110_001 60.0 80.0 2.5 150.0 200.0 3 180.0 240.0 3 50.0 66.7 0110_010 60.0 80.0 2.5 150.0 200.0 3.5 210.0 280.0 3 50.0 66.7 0110_011 60.0 80.0 2.5 150.0 200.0 4 240.0 320.0 3 50.0 66.7 0110_100 60.0 80.0 2.5 150.0 200.0 4.5 270.0 360.0 3 50.0 66.7 0110_101 60.0 80.0 2.5 150.0 200.0 5 300.0 400.0 3 50.0 66.7 0110_110 60.0 80.0 2.5 150.0 200.0 6 360.0 480.0 3 50.0 66.7 0111_000 reserved 0111_001 50.0 66.7 3 150.0 200.0 3 150.0 200.0 3 50.0 66.7 0111_010 50.0 66.7 3 150.0 200.0 3.5 175.0 233.3 3 50.0 66.7 0111_011 50.0 66.7 3 150.0 200.0 4 200.0 266.6 3 50.0 66.7 table 16. clock configurations for pci host mode (pci_modck=0) 1, 2 (continued) mode 3 bus clock 4 (mhz) cpm multiplication factor 5 cpm clock (mhz) cpu multiplication factor 6 cpu clock (mhz) pci division factor pci clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 29 clock configuration modes 0111_100 50.0 66.7 3 150.0 200.0 4.5 225.0 300.0 3 50.0 66.7 1000_000 reserved 1000_001 66.7 88.9 3 200.0 266.6 3 200.0 266.6 4 50.0 66.7 1000_010 66.7 88.9 3 200.0 266.6 3.5 233.3 311.1 4 50.0 66.7 1000_011 66.7 88.9 3 200.0 266.6 4 266.7 355.5 4 50.0 66.7 1000_100 66.7 88.9 3 200.0 266.6 4.5 300.0 400.0 4 50.0 66.7 1000_101 66.7 88.9 3 200.0 266.6 6 400.0 533.3 4 50.0 66.7 1000_110 66.7 88.9 3 200.0 266.6 6.5 433.3 577.7 4 50.0 66.7 1001_000 reserved 1001_001 reserved 1001_010 57.1 76.2 3.5 200.0 266.6 3.5 200.0 266.6 4 50.0 66.7 1001_011 57.1 76.2 3.5 200.0 266.6 4 228.6 304.7 4 50.0 66.7 1001_100 57.1 76.2 3.5 200.0 266.6 4.5 257.1 342.8 4 50.0 66.7 1001_101 85.7 114.3 3.5 300.0 400.0 5 428.6 571.4 6 50.0 66.7 1001_110 85.7 114.3 3.5 300.0 400.0 5.5 471.4 628.5 6 50.0 66.7 1001_111 85.7 114.3 3.5 300.0 400.0 6 514.3 685.6 6 50.0 66.7 1010_000 75.0 100.0 2 150.0 200.0 2 150.0 200.0 3 50.0 66.7 1010_001 75.0 100.0 2 150.0 200.0 2.5 187.5 250.0 3 50.0 66.7 1010_010 75.0 100.0 2 150.0 200.0 3 225.0 300.0 3 50.0 66.7 1010_011 75.0 100.0 2 150.0 200.0 3.5 262.5 350.0 3 50.0 66.7 1010_100 75.0 100.0 2 150.0 200.0 4 300.0 400.0 3 50.0 66.7 1011_000 reserved 1011_001 80.0 106.7 2.5 200.0 266.6 2.5 200.0 266.6 4 50.0 66.7 1011_010 80.0 106.7 2.5 200.0 266.6 3 240.0 320.0 4 50.0 66.7 1011_011 80.0 106.7 2.5 200.0 266.6 3.5 280.0 373.3 4 50.0 66.7 1011_100 80.0 106.7 2.5 200.0 266.6 4 320.0 426.6 4 50.0 66.7 1011_101 80.0 106.7 2.5 200.0 266.6 4.5 360.0 480.0 4 50.0 66.7 table 16. clock configurations for pci host mode (pci_modck=0) 1, 2 (continued) mode 3 bus clock 4 (mhz) cpm multiplication factor 5 cpm clock (mhz) cpu multiplication factor 6 cpu clock (mhz) pci division factor pci clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 30 freescale semiconductor clock configuration modes 1101_000 100.0 133.3 2.5 250.0 333.3 3 300.0 400.0 5 50.0 66.7 1101_001 100.0 133.3 2.5 250.0 333.3 3.5 350.0 466.6 5 50.0 66.7 1101_010 100.0 133.3 2.5 250.0 333.3 4 400.0 533.3 5 50.0 66.7 1101_011 100.0 133.3 2.5 250.0 333.3 4.5 450.0 599.9 5 50.0 66.7 1101_100 100.0 133.3 2.5 250.0 333.3 5 500.0 666.6 5 50.0 66.7 1101_101 125.0 166.7 2 250.0 333.3 3 375.0 500.0 5 50.0 66.7 1101_110 125.0 166.7 2 250.0 333.3 4 500.0 666.6 5 50.0 66.7 1110_000 100.0 133.3 3 300.0 400.0 3.5 350.0 466.6 6 50.0 66.7 1110_001 100.0 133.3 3 300.0 400.0 4 400.0 533.3 6 50.0 66.7 1110_010 100.0 133.3 3 300.0 400.0 4.5 450.0 599.9 6 50.0 66.7 1110_011 100.0 133.3 3 300.0 400.0 5 500.0 666.6 6 50.0 66.7 1110_100 100.0 133.3 3 300.0 400.0 5.5 550.0 733.3 6 50.0 66.7 1100_000 reserved 1100_001 reserved 1100_010 reserved 1 the ?low? values are the minimum allowable frequencies for a given clock mode. the minimum bus frequency in a table entry guarantees only the required minimum cpu operating frequency. the ?high? values are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configuration does not violate the frequency rating of the user?s device. the minimum cpm frequency is 120 mhz. minimum cpu frequency is determined by the clock mode. for modes with a cpu multiplication factor <= 3, the minimum cpu frequency is 150 mhz for commercial temperature devices and 175 mhz for extended temperature devices. for modes with a cpu multiplication factor >= 3.5: for rev0.1 the minimum cpu frequency is 250 mhz; for reva or later the minimum cpu frequency is 150 mhz for commercial temperature devices and 175 mhz for extended temperature devices. 2 as ta b l e 1 4 shows, pci_modck determines the pci clock frequency range. refer to ta b l e 1 7 for lower configurations. 3 modck_h = hard reset configuration word [28?31]. modck[1-3] = three hardware configuration pins. 4 60x and local bus frequency. identical to clkin. 5 cpm multiplication factor = cpm clock/bus clock 6 cpu multiplication factor = core pll multiplication factor table 16. clock configurations for pci host mode (pci_modck=0) 1, 2 (continued) mode 3 bus clock 4 (mhz) cpm multiplication factor 5 cpm clock (mhz) cpu multiplication factor 6 cpu clock (mhz) pci division factor pci clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 31 clock configuration modes table 17. clock configurations for pci host mode (pci_modck=1) 1, 2 mode 3 bus clock 4 (mhz) cpm multiplication factor 5 cpm clock (mhz) cpu multiplication factor 6 cpu clock (mhz) pci division factor pci clock (mhz) modck_h- modck[1-3] low high low high low high low high default modes (modck_h=0000) 0000_000 60.0 100.0 2 120.0 200.0 2.5 150.0 250.0 4 30.0 50.0 0000_001 50.0 100.0 2 100.0 200.0 3 150.0 300.0 4 25.0 50.0 0000_010 60.0 120.0 2.5 150.0 300.0 3 180.0 360.0 6 25.0 50.0 0000_011 60.0 120.0 2.5 150.0 300.0 3.5 210.0 420.0 6 25.0 50.0 0000_100 60.0 120.0 2.5 150.0 300.0 4 240.0 480.0 6 25.0 50.0 0000_101 50.0 100.0 3 150.0 300.0 3 150.0 300.0 6 25.0 50.0 0000_110 50.0 100.0 3 150.0 300.0 3.5 175.0 350.0 6 25.0 50.0 0000_111 50.0 100.0 3 150.0 300.0 4 200.0 400.0 6 25.0 50.0 full configuration modes 0001_000 50.0 100.0 3 150.0 300.0 5 250.0 500.0 6 25.0 50.0 0001_001 50.0 100.0 3 150.0 300.0 6 300.0 600.0 6 25.0 50.0 0001_010 50.0 100.0 3 150.0 300.0 7 350.0 700.0 6 25.0 50.0 0001_011 50.0 100.0 3 150.0 300.0 8 400.0 800.0 6 25.0 50.0 0010_000 50.0 100.0 4 200.0 400.0 5 250.0 500.0 8 25.0 50.0 0010_001 50.0 100.0 4 200.0 400.0 6 300.0 600.0 8 25.0 50.0 0010_010 50.0 100.0 4 200.0 400.0 7 350.0 700.0 8 25.0 50.0 0010_011 50.0 100.0 4 200.0 400.0 8 400.0 800.0 8 25.0 50.0 0010_100 37.5 75.0 4 150.0 300.0 5 187.5 375.0 6 25.0 50.0 0010_101 37.5 75.0 4 150.0 300.0 5.5 206.3 412.5 6 25.0 50.0 0010_110 37.5 75.0 4 150.0 300.0 6 225.0 450.0 6 25.0 50.0 0011_000 30.0 50.0 5 150.0 250.0 5 150.0 250.0 5 30.0 50.0 0011_001 25.0 50.0 5 125.0 250.0 6 150.0 300.0 5 25.0 50.0 0011_010 25.0 50.0 5 125.0 250.0 7 175.0 350.0 5 25.0 50.0 0011_011 25.0 50.0 5 125.0 250.0 8 200.0 400.0 5 25.0 50.0 0100_000 reserved 0100_001 25.0 50.0 6 150.0 300.0 6 150.0 300.0 6 25.0 50.0 0100_010 25.0 50.0 6 150.0 300.0 7 175.0 350.0 6 25.0 50.0
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 32 freescale semiconductor clock configuration modes 0100_011 25.0 50.0 6 150.0 300.0 8 200.0 400.0 6 25.0 50.0 0101_000 60.0 100.0 2 120.0 200.0 2.5 150.0 250.0 4 30.0 50.0 0101_001 50.0 100.0 2 100.0 200.0 3 150.0 300.0 4 25.0 50.0 0101_010 50.0 100.0 2 100.0 200.0 3.5 175.0 350.0 4 25.0 50.0 0101_011 50.0 100.0 2 100.0 200.0 4 200.0 400.0 4 25.0 50.0 0101_100 50.0 100.0 2 100.0 200.0 4.5 225.0 450.0 4 25.0 50.0 0110_000 60.0 120.0 2.5 150.0 300.0 2.5 150.0 300.0 6 25.0 50.0 0110_001 60.0 120.0 2.5 150.0 300.0 3 180.0 360.0 6 25.0 50.0 0110_010 60.0 120.0 2.5 150.0 300.0 3.5 210.0 420.0 6 25.0 50.0 0110_011 60.0 120.0 2.5 150.0 300.0 4 240.0 480.0 6 25.0 50.0 0110_100 60.0 120.0 2.5 150.0 300.0 4.5 270.0 540.0 6 25.0 50.0 0110_101 60.0 120.0 2.5 150.0 300.0 5 300.0 600.0 6 25.0 50.0 0110_110 60.0 120.0 2.5 150.0 300.0 6 360.0 720.0 6 25.0 50.0 0111_000 reserved 0111_001 50.0 100.0 3 150.0 300.0 3 150.0 300.0 6 25.0 50.0 0111_010 50.0 100.0 3 150.0 300.0 3.5 175.0 350.0 6 25.0 50.0 0111_011 50.0 100.0 3 150.0 300.0 4 200.0 400.0 6 25.0 50.0 0111_100 50.0 100.0 3 150.0 300.0 4.5 225.0 450.0 6 25.0 50.0 1000_000 reserved 1000_001 66.7 133.3 3 200.0 400.0 3 200.0 400.0 8 25.0 50.0 1000_010 66.7 133.3 3 200.0 400.0 3.5 233.3 466.7 8 25.0 50.0 1000_011 66.7 133.3 3 200.0 400.0 4 266.7 533.3 8 25.0 50.0 1000_100 66.7 133.3 3 200.0 400.0 4.5 300.0 600.0 8 25.0 50.0 1000_101 66.7 133.3 3 200.0 400.0 6 400.0 800.0 8 25.0 50.0 1000_110 66.7 133.3 3 200.0 400.0 6.5 433.3 866.7 8 25.0 50.0 1001_000 reserved 1001_001 reserved table 17. clock configurations for pci host mode (pci_modck=1) 1, 2 (continued) mode 3 bus clock 4 (mhz) cpm multiplication factor 5 cpm clock (mhz) cpu multiplication factor 6 cpu clock (mhz) pci division factor pci clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 33 clock configuration modes 1001_010 57.1 114.3 3.5 200.0 400.0 3.5 200.0 400.0 8 25.0 50.0 1001_011 57.1 114.3 3.5 200.0 400.0 4 228.6 457.1 8 25.0 50.0 1001_100 57.1 114.3 3.5 200.0 400.0 4.5 257.1 514.3 8 25.0 50.0 1001_101 42.9 85.7 3.5 150.0 300.0 5 214.3 428.6 6 25.0 50.0 1001_110 42.9 85.7 3.5 150.0 300.0 5.5 235.7 471.4 6 25.0 50.0 1001_111 42.9 85.7 3.5 150.0 300.0 6 257.1 514.3 6 25.0 50.0 1010_000 75.0 150.0 2 150.0 300.0 2 150.0 300.0 6 25.0 50.0 1010_001 75.0 150.0 2 150.0 300.0 2.5 187.5 375.0 6 25.0 50.0 1010_010 75.0 150.0 2 150.0 300.0 3 225.0 450.0 6 25.0 50.0 1010_011 75.0 150.0 2 150.0 300.0 3.5 262.5 525.0 6 25.0 50.0 1010_100 75.0 150.0 2 150.0 300.0 4 300.0 600.0 6 25.0 50.0 1011_000 reserved 1011_001 80.0 160.0 2.5 200.0 400.0 2.5 200.0 400.0 8 25.0 50.0 1011_010 80.0 160.0 2.5 200.0 400.0 3 240.0 480.0 8 25.0 50.0 1011_011 80.0 160.0 2.5 200.0 400.0 3.5 280.0 560.0 8 25.0 50.0 1011_100 80.0 160.0 2.5 200.0 400.0 4 320.0 640.0 8 25.0 50.0 1011_101 80.0 160.0 2.5 200.0 400.0 4.5 360.0 720.0 8 25.0 50.0 1101_000 50.0 100.0 2.5 125.0 250.0 3 150.0 300.0 5 25.0 50.0 1101_001 50.0 100.0 2.5 125.0 250.0 3.5 175.0 350.0 5 25.0 50.0 1101_010 50.0 100.0 2.5 125.0 250.0 4 200.0 400.0 5 25.0 50.0 1101_011 50.0 100.0 2.5 125.0 250.0 4.5 225.0 450.0 5 25.0 50.0 1101_100 50.0 100.0 2.5 125.0 250.0 5 250.0 500.0 5 25.0 50.0 1101_101 62.5 125.0 2 125.0 250.0 3 187.5 375.0 5 25.0 50.0 1101_110 62.5 125.0 2 125.0 250.0 4 250.0 500.0 5 25.0 50.0 1110_000 50.0 100.0 3 150.0 300.0 3.5 175.0 350.0 6 25.0 50.0 1110_001 50.0 100.0 3 150.0 300.0 4 200.0 400.0 6 25.0 50.0 table 17. clock configurations for pci host mode (pci_modck=1) 1, 2 (continued) mode 3 bus clock 4 (mhz) cpm multiplication factor 5 cpm clock (mhz) cpu multiplication factor 6 cpu clock (mhz) pci division factor pci clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 34 freescale semiconductor clock configuration modes 7.3 pci agent mode table 18 and table 19 show configurations for pci agent mode. the frequencies listed are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user?s device. in addition, note the following: note: pci_modck in pci mode only, pci_modck comes from the lgpl5 pin and modck_h[0?3] comes from {lgpl0, lgpl1, lgpl2, lgpl3}. note: tval (output hold) the minimum tval = 2 ns when pci_modck = 1, and the minimum tval = 1 ns when pci_modck = 0. therefore, designers should use clock configurations that fit this condition to achieve pci-compliant ac timing. 1110_010 50.0 100.0 3 150.0 300.0 4.5 225.0 450.0 6 25.0 50.0 1110_011 50.0 100.0 3 150.0 300.0 5 250.0 500.0 6 25.0 50.0 1110_100 50.0 100.0 3 150.0 300.0 5.5 275.0 550.0 6 25.0 50.0 1100_000 reserved 1100_001 reserved 1100_010 reserved 1 the ?low? values are the minimum allowable frequencies for a given clock mode. the minimum bus frequency in a table entry guarantees only the required minimum cpu operating frequency. the ?high? values are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configuration does not violate the frequency rating of the user?s device. the minimum cpm frequency is 120 mhz. minimum cpu frequency is determined by the clock mode. for modes with a cpu multiplication factor <= 3, the minimum cpu frequency is 150 mhz for commercial temperature devices and 175 mhz for extended temperature devices. for modes with a cpu multiplication factor >= 3.5: for rev0.1 the minimum cpu frequency is 250 mhz; for reva or later the minimum cpu frequency is 150 mhz for commercial temperature devices and 175 mhz for extended temperature devices. 2 as ta b l e 1 4 shows, pci_modck determines the pci clock frequency range. refer to ta ble 1 6 for higher configurations. 3 modck_h = hard reset configuration word [28?31]. modck[1-3] = three hardware configuration pins. 4 60x and local bus frequency. identical to clkin. 5 cpm multiplication factor = cpm clock/bus clock 6 cpu multiplication factor = core pll multiplication factor table 17. clock configurations for pci host mode (pci_modck=1) 1, 2 (continued) mode 3 bus clock 4 (mhz) cpm multiplication factor 5 cpm clock (mhz) cpu multiplication factor 6 cpu clock (mhz) pci division factor pci clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 35 clock configuration modes table 18. clock configurations for pci agent mode (pci_modck=0) 1, 2 mode 3 pci clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) bus division factor bus clock (mhz) modck_h- modck[1-3] low high low high low high low high default modes (modck_h=0000 0000_000 60.0 66.7 2 120.0 133.3 2.5 150.0 166.7 2 60.0 66.7 0000_001 50.0 66.7 2 100.0 133.3 3 150.0 200.0 2 50.0 66.7 0000_010 50.0 66.7 3 150.0 200.0 3 150.0 200.0 3 50.0 66.7 0000_011 50.0 66.7 3 150.0 200.0 4 200.0 266.6 3 50.0 66.7 0000_100 50.0 66.7 3 150.0 200.0 3 180.0 240.0 2.5 60.0 80.0 0000_101 50.0 66.7 3 150.0 200.0 3.5 210.0 280.0 2.5 60.0 80.0 0000_110 50.0 66.7 4 200.0 266.6 3.5 233.3 311.1 3 66.7 88.9 0000_111 50.0 66.7 4 200.0 266.6 3 240.0 320.0 2.5 80.0 106.7 full configuration modes 0001_001 60.0 66.7 2 120.0 133.3 5 150.0 166.7 4 30.0 33.3 0001_010 50.0 66.7 2 100.0 133.3 6 150.0 200.0 4 25.0 33.3 0001_011 50.0 66.7 2 100.0 133.3 7 175.0 233.3 4 25.0 33.3 0001_100 50.0 66.7 2 100.0 133.3 8 200.0 266.6 4 25.0 33.3 0010_001 50.0 66.7 3 150.0 200.0 3 180.0 240.0 2.5 60.0 80.0 0010_010 50.0 66.7 3 150.0 200.0 3.5 210.0 280.0 2.5 60.0 80.0 0010_011 50.0 66.7 3 150.0 200.0 4 240.0 320.0 2.5 60.0 80.0 0010_100 50.0 66.7 3 150.0 200.0 4.5 270.0 360.0 2.5 60.0 80.0 0011_000 reserved 0011_001 reserved 0011_010 reserved 0011_011 reserved 0011_100 reserved 0100_000 reserved 0100_001 50.0 66.7 3 150.0 200.0 3 150.0 200.0 3 50.0 66.7 0100_010 50.0 66.7 3 150.0 200.0 3.5 175.0 200.0 3 50.0 66.7 0100_011 50.0 66.7 3 150.0 200.0 4 200.0 266.6 3 50.0 66.7 0100_100 50.0 66.7 3 150.0 200.0 4.5 225.0 300.0 3 50.0 66.7
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 36 freescale semiconductor clock configuration modes 0101_000 50.0 66.7 5 250.0 333.3 2.5 250.0 333.3 2.5 100.0 133.3 0101_001 50.0 66.7 5 250.0 333.3 3 300.0 400.0 2.5 100.0 133.3 0101_010 50.0 66.7 5 250.0 333.3 3.5 350.0 466.6 2.5 100.0 133.3 0101_011 50.0 66.7 5 250.0 333.3 4 400.0 533.3 2.5 100.0 133.3 0101_100 50.0 66.7 5 250.0 333.3 4.5 450.0 599.9 2.5 100.0 133.3 0101_101 50.0 66.7 5 250.0 333.3 5 500.0 666.6 2.5 100.0 133.3 0101_110 50.0 66.7 5 250.0 333.3 5.5 550.0 733.3 2.5 100.0 133.3 0110_000 reserved 0110_001 50.0 66.7 4 200.0 266.6 3 200.0 266.6 3 66.7 88.9 0110_010 50.0 66.7 4 200.0 266.6 3.5 233.3 311.1 3 66.7 88.9 0110_011 50.0 66.7 4 200.0 266.6 4 266.7 355.5 3 66.7 88.9 0110_100 50.0 66.7 4 200.0 266.6 4.5 300.0 400.0 3 66.7 88.9 0111_000 50.0 66.7 3 150.0 200.0 2 150.0 200.0 2 75.0 100.0 0111_001 50.0 66.7 3 150.0 200.0 2.5 187.5 250.0 2 75.0 100.0 0111_010 50.0 66.7 3 150.0 200.0 3 225.0 300.0 2 75.0 100.0 0111_011 50.0 66.7 3 150.0 200.0 3.5 262.5 350.0 2 75.0 100.0 1000_000 reserved 1000_001 50.0 66.7 3 150.0 200.0 2.5 150.0 166.7 2.5 60.0 80.0 1000_010 50.0 66.7 3 150.0 200.0 3 180.0 240.0 2.5 60.0 80.0 1000_011 50.0 66.7 3 150.0 200.0 3.5 210.0 280.0 2.5 60.0 80.0 1000_100 50.0 66.7 3 150.0 200.0 4 240.0 320.0 2.5 60.0 80.0 1000_101 50.0 66.7 3 150.0 200.0 4.5 270.0 360.0 2.5 60.0 80.0 1001_000 reserved 1001_001 reserved 1001_010 reserved 1001_011 50.0 66.7 4 200.0 266.6 4 200.0 266.6 4 50.0 66.7 1001_100 50.0 66.7 4 200.0 266.6 4.5 225.0 300.0 4 50.0 66.7 table 18. clock configurations for pci agent mode (pci_modck=0) 1, 2 (continued) mode 3 pci clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) bus division factor bus clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 37 clock configuration modes 1010_000 reserved 1010_001 50.0 66.7 4 200.0 266.6 3 200.0 266.6 3 66.7 88.9 1010_010 50.0 66.7 4 200.0 266.6 3.5 233.3 311.1 3 66.7 88.9 1010_011 50.0 66.7 4 200.0 266.6 4 266.7 355.5 3 66.7 88.9 1010_100 50.0 66.7 4 200.0 266.6 4.5 300.0 400.0 3 66.7 88.9 1011_000 reserved 1011_001 50.0 66.7 4 200.0 266.6 2.5 200.0 266.6 2.5 80.0 106.7 1011_010 50.0 66.7 4 200.0 266.6 3 240.0 320.0 2.5 80.0 106.7 1011_011 50.0 66.7 4 200.0 266.6 3.5 280.0 373.3 2.5 80.0 106.7 1011_100 50.0 66.7 4 200.0 266.6 4 320.0 426.6 2.5 80.0 106.7 1100_101 50.0 66.7 6 300.0 400.0 4 400.0 533.3 3 100.0 133.3 1100_110 50.0 66.7 6 300.0 400.0 4.5 450.0 599.9 3 100.0 133.3 1100_111 50.0 66.7 6 300.0 400.0 5 500.0 666.6 3 100.0 133.3 1101_000 50.0 66.7 6 300.0 400.0 5.5 550.0 733.3 3 100.0 133.3 1101_001 50.0 66.7 6 300.0 400.0 3.5 420.0 559.9 2.5 120.0 160.0 1101_010 50.0 66.7 6 300.0 400.0 4 480.0 639.9 2.5 120.0 160.0 1101_011 50.0 66.7 6 300.0 400.0 4.5 540.0 719.9 2.5 120.0 160.0 1101_100 50.0 66.7 6 300.0 400.0 5 600.0 799.9 2.5 120.0 160.0 1110_000 50.0 66.7 5 250.0 333.3 2.5 312.5 416.6 2 125.0 166.7 1110_001 50.0 66.7 5 250.0 333.3 3 375.0 500.0 2 125.0 166.7 1110_010 50.0 66.7 5 250.0 333.3 3.5 437.5 583.3 2 125.0 166.7 1110_011 50.0 66.7 5 250.0 333.3 4 500.0 666.6 2 125.0 166.7 1110_100 50.0 66.7 5 250.0 333.3 4 333.3 444.4 3 83.3 111.1 1110_101 50.0 66.7 5 250.0 333.3 4.5 375.0 500.0 3 83.3 111.1 1110_110 50.0 66.7 5 250.0 333.3 5 416.7 555.5 3 83.3 111.1 1110_111 50.0 66.7 5 250.0 333.3 5.5 458.3 611.1 3 83.3 111.1 table 18. clock configurations for pci agent mode (pci_modck=0) 1, 2 (continued) mode 3 pci clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) bus division factor bus clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 38 freescale semiconductor clock configuration modes 1100_000 reserved 1100_001 reserved 1100_010 reserved 1 the ?low? values are the minimum allowable frequencies for a given clock mode. the minimum bus frequency in a table entry guarantees only the required minimum cpu operating frequency. the ?high? values are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configuration does not violate the frequency rating of the user?s device. the minimum cpm frequency is 120 mhz. minimum cpu frequency is determined by the clock mode. for modes with a cpu multiplication factor <= 3, the minimum cpu frequency is 150 mhz for commercial temperature devices and 175 mhz for extended temperature devices. for modes with a cpu multiplication factor >= 3.5: for rev0.1 the minimum cpu frequency is 250 mhz; for reva or later the minimum cpu frequency is 150 mhz for commercial temperature devices and 175 mhz for extended temperature devices. 2 as shown in ta b l e 1 4 , pci_modck determines the pci clock frequency range. refer to table 19 for lower configurations. 3 modck_h = hard reset configuration word [28?31]. modck[1-3] = three hardware configuration pins. 4 cpm multiplication factor = cpm clock/pci clock 5 cpu multiplication factor = core pll multiplication factor table 19. clock configurations for pci agent mode (pci_modck=1) 1, 2 mode 3 pci clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) bus division factor bus clock (mhz) modck_h- modck[1-3] low high low high low high low high default modes (modck_h=0000) 0000_000 30.0 50.0 4 120.0 200.0 2.5 150.0 250.0 2 60.0 100.0 0000_001 25.0 50.0 4 100.0 200.0 3 150.0 300.0 2 50.0 100.0 0000_010 25.0 50.0 6 150.0 300.0 3 150.0 300.0 3 50.0 100.0 0000_011 25.0 50.0 6 150.0 300.0 4 200.0 400.0 3 50.0 100.0 0000_100 25.0 50.0 6 150.0 300.0 3 180.0 360.0 2.5 60.0 120.0 0000_101 25.0 50.0 6 150.0 300.0 3.5 210.0 420.0 2.5 60.0 120.0 0000_110 25.0 50.0 8 200.0 400.0 3.5 233.3 466.7 3 66.7 133.3 0000_111 25.0 50.0 8 200.0 400.0 3 240.0 480.0 2.5 80.0 160.0 full configuration modes 0001_001 30.0 50.0 4 120.0 200.0 5 150.0 250.0 4 30.0 50.0 0001_010 25.0 50.0 4 100.0 200.0 6 150.0 300.0 4 25.0 50.0 0001_011 25.0 50.0 4 100.0 200.0 7 175.0 350.0 4 25.0 50.0 table 18. clock configurations for pci agent mode (pci_modck=0) 1, 2 (continued) mode 3 pci clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) bus division factor bus clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 39 clock configuration modes 0001_100 25.0 50.0 4 100.0 200.0 8 200.0 400.0 4 25.0 50.0 0010_001 25.0 50.0 6 150.0 300.0 3 180.0 360.0 2.5 60.0 120.0 0010_010 25.0 50.0 6 150.0 300.0 3.5 210.0 420.0 2.5 60.0 120.0 0010_011 25.0 50.0 6 150.0 300.0 4 240.0 480.0 2.5 60.0 120.0 0010_100 25.0 50.0 6 150.0 300.0 4.5 270.0 540.0 2.5 60.0 120.0 0011_000 reserved 0011_001 37.5 50.0 4 150.0 200.0 3 150.0 200.0 3 50.0 66.7 0011_010 32.1 50.0 4 128.6 200.0 3.5 150.0 233.3 3 42.9 66.7 0011_011 28.1 50.0 4 112.5 200.0 4 150.0 266.7 3 37.5 66.7 0011_100 25.0 50.0 4 100.0 200.0 4.5 150.0 300.0 3 33.3 66.7 0100_000 reserved 0100_001 25.0 50.0 6 150.0 300.0 3 150.0 300.0 3 50.0 100.0 0100_010 25.0 50.0 6 150.0 300.0 3.5 175.0 350.0 3 50.0 100.0 0100_011 25.0 50.0 6 150.0 300.0 4 200.0 400.0 3 50.0 100.0 0100_100 25.0 50.0 6 150.0 300.0 4.5 225.0 450.0 3 50.0 100.0 0101_000 30.0 50.0 5 150.0 250.0 2.5 150.0 250.0 2.5 60.0 100.0 0101_001 25.0 50.0 5 125.0 250.0 3 150.0 300.0 2.5 50.0 100.0 0101_010 25.0 50.0 5 125.0 250.0 3.5 175.0 350.0 2.5 50.0 100.0 0101_011 25.0 50.0 5 125.0 250.0 4 200.0 400.0 2.5 50.0 100.0 0101_100 25.0 50.0 5 125.0 250.0 4.5 225.0 450.0 2.5 50.0 100.0 0101_101 25.0 50.0 5 125.0 250.0 5 250.0 500.0 2.5 50.0 100.0 0101_110 25.0 50.0 5 125.0 250.0 5.5 275.0 550.0 2.5 50.0 100.0 0110_000 reserved 0110_001 25.0 50.0 8 200.0 400.0 3 200.0 400.0 3 66.7 133.3 0110_010 25.0 50.0 8 200.0 400.0 3.5 233.3 466.7 3 66.7 133.3 0110_011 25.0 50.0 8 200.0 400.0 4 266.7 533.3 3 66.7 133.3 0110_100 25.0 50.0 8 200.0 400.0 4.5 300.0 600.0 3 66.7 133.3 table 19. clock configurations for pci agent mode (pci_modck=1) 1, 2 (continued) mode 3 pci clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) bus division factor bus clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 40 freescale semiconductor clock configuration modes 0111_000 25.0 50.0 6 150.0 300.0 2 150.0 300.0 2 75.0 150.0 0111_001 25.0 50.0 6 150.0 300.0 2.5 187.5 375.0 2 75.0 150.0 0111_010 25.0 50.0 6 150.0 300.0 3 225.0 450.0 2 75.0 150.0 0111_011 25.0 50.0 6 150.0 300.0 3.5 262.5 525.0 2 75.0 150.0 1000_000 reserved 1000_001 25.0 50.0 6 150.0 300.0 2.5 150.0 300.0 2.5 60.0 120.0 1000_010 25.0 50.0 6 150.0 300.0 3 180.0 360.0 2.5 60.0 120.0 1000_011 25.0 50.0 6 150.0 300.0 3.5 210.0 420.0 2.5 60.0 120.0 1000_100 25.0 50.0 6 150.0 300.0 4 240.0 480.0 2.5 60.0 120.0 1000_101 25.0 50.0 6 150.0 300.0 4.5 270.0 540.0 2.5 60.0 120.0 1001_000 reserved 1001_001 reserved 1001_010 reserved 1001_011 25.0 50.0 8 200.0 400.0 4 200.0 400.0 4 50.0 100.0 1001_100 25.0 50.0 8 200.0 400.0 4.5 225.0 450.0 4 50.0 100.0 1010_000 reserved 1010_001 25.0 50.0 8 200.0 400.0 3 200.0 400.0 3 66.7 133.3 1010_010 25.0 50.0 8 200.0 400.0 3.5 233.3 466.7 3 66.7 133.3 1010_011 25.0 50.0 8 200.0 400.0 4 266.7 533.3 3 66.7 133.3 1010_100 25.0 50.0 8 200.0 400.0 4.5 300.0 600.0 3 66.7 133.3 1011_000 reserved 1011_001 25.0 50.0 8 200.0 400.0 2.5 200.0 400.0 2.5 80.0 160.0 1011_010 25.0 50.0 8 200.0 400.0 3 240.0 480.0 2.5 80.0 160.0 1011_011 25.0 50.0 8 200.0 400.0 3.5 280.0 560.0 2.5 80.0 160.0 1011_100 25.0 50.0 8 200.0 400.0 4 320.0 640.0 2.5 80.0 160.0 1100_101 25.0 50.0 6 150.0 300.0 4 200.0 400.0 3 50.0 100.0 table 19. clock configurations for pci agent mode (pci_modck=1) 1, 2 (continued) mode 3 pci clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) bus division factor bus clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 41 clock configuration modes 1100_110 25.0 50.0 6 150.0 300.0 4.5 225.0 450.0 3 50.0 100.0 1100_111 25.0 50.0 6 150.0 300.0 5 250.0 500.0 3 50.0 100.0 1101_000 25.0 50.0 6 150.0 300.0 5.5 275.0 550.0 3 50.0 100.0 1101_001 25.0 50.0 6 150.0 300.0 3.5 210.0 420.0 2.5 60.0 120.0 1101_010 25.0 50.0 6 150.0 300.0 4 240.0 480.0 2.5 60.0 120.0 1101_011 25.0 50.0 6 150.0 300.0 4.5 270.0 540.0 2.5 60.0 120.0 1101_100 25.0 50.0 6 150.0 300.0 5 300.0 600.0 2.5 60.0 120.0 1110_000 25.0 50.0 5 125.0 250.0 2.5 156.3 312.5 2 62.5 125.0 1110_001 25.0 50.0 5 125.0 250.0 3 187.5 375.0 2 62.5 125.0 1110_010 25.0 50.0 5 125.0 250.0 3.5 218.8 437.5 2 62.5 125.0 1110_011 25.0 50.0 5 125.0 250.0 4 250.0 500.0 2 62.5 125.0 1110_100 25.0 50.0 5 125.0 250.0 4 166.7 333.3 3 41.7 83.3 1110_101 25.0 50.0 5 125.0 250.0 4.5 187.5 375.0 3 41.7 83.3 1110_110 25.0 50.0 5 125.0 250.0 5 208.3 416.7 3 41.7 83.3 1110_111 25.0 50.0 5 125.0 250.0 5.5 229.2 458.3 3 41.7 83.3 1100_000 reserved 1100_001 reserved 1100_010 reserved 1 the ?low? values are the minimum allowable frequencies for a given clock mode. the minimum bus frequency in a table entry guarantees only the required minimum cpu operating frequency. the ?high? values are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configuration does not violate the frequency rating of the user?s device. the minimum cpm frequency is 120 mhz. minimum cpu frequency is determined by the clock mode. for modes with a cpu multiplication factor <= 3, the minimum cpu frequency is 150 mhz for commercial temperature devices and 175 mhz for extended temperature devices. for modes with a cpu multiplication factor >= 3.5: for rev0.1 the minimum cpu frequency is 250 mhz; for reva or later the minimum cpu frequency is 150 mhz for commercial temperature devices and 175 mhz for extended temperature devices. 2 as shown in ta b l e 1 4 , pci_modck determines the pci clock range. refer to ta b l e 1 8 for higher range configurations. 3 modck_h = hard reset configuration word [28?31]. modck[1-3] = three hardware configuration pins. 4 cpm multiplication factor = cpm clock/pci clock 5 cpu multiplication factor = core pll multiplication factor table 19. clock configurations for pci agent mode (pci_modck=1) 1, 2 (continued) mode 3 pci clock (mhz) cpm multiplication factor 4 cpm clock (mhz) cpu multiplication factor 5 cpu clock (mhz) bus division factor bus clock (mhz) modck_h- modck[1-3] low high low high low high low high
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 42 freescale semiconductor pinout 8 pinout this section provides the pin assignments and pinout lists for both hip7 powerquicc ii packages. 8.1 zu package?mpc8280 and MPC8270 the following figures and table represent the standard 480 tbga package. for information on the alternate package, refer to section 8.2, ?vr and zq packages?mpc8275 and MPC8270? on page 57. figure 13 shows the pinout of the zu package as viewed from the top surface. figure 13. pinout of the 480 tbga package (view from top) 1 2 3 4 5 6 7 8 910111213141516 17 18 19 20 21 22 23 24 25 26 27 28 29 not to scale 1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 43 pinout figure 14 shows the side profile of the tbga package to indicate the direction of the top surface view. figure 14. side view of the tbga package table 20 shows the pinout list of the mpc8280 and MPC8270. table 21 defines conventions and acronyms used in table 20 . table 20. mpc8280 and MPC8270 (zu package) pinout list pin name ball mpc8280/MPC8270 mpc8280 only br w5 bg f4 abb /irq2 e2 ts e3 a0 g1 a1 h5 a2 h2 a3 h1 a4 j5 a5 j4 a6 j3 a7 j2 a8 j1 a9 k4 a10 k3 a11 k2 a12 k1 a13 l5 a14 l4 a15 l3 a16 l2 soldermask copper traces die copper heat spreader (oxidized for insulation) 1.27 mm pitch glob-top dam wire bonds etched pressure sensitive die glob-top filled area polymide tape cavity adhesive attach view
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 44 freescale semiconductor pinout a17 l1 a18 m5 a19 n5 a20 n4 a21 n3 a22 n2 a23 n1 a24 p4 a25 p3 a26 p2 a27 p1 a28 r1 a29 r3 a30 r5 a31 r4 tt0 f1 tt1 g4 tt2 g3 tt3 g2 tt4 f2 tbst d3 tsiz0 c1 tsiz1 e4 tsiz2 d2 tsiz3 f5 aack f3 artry e1 dbg v1 dbb /irq3 v2 d0 b20 d1 a18 d2 a16 d3 a13 table 20. mpc8280 and MPC8270 (zu package) pinout list (continued) pin name ball mpc8280/MPC8270 mpc8280 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 45 pinout d4 e12 d5 d9 d6 a6 d7 b5 d8 a20 d9 e17 d10 b15 d11 b13 d12 a11 d13 e9 d14 b7 d15 b4 d16 d19 d17 d17 d18 d15 d19 c13 d20 b11 d21 a8 d22 a5 d23 c5 d24 c19 d25 c17 d26 c15 d27 d13 d28 c11 d29 b8 d30 a4 d31 e6 d32 e18 d33 b17 d34 a15 d35 a12 d36 d11 table 20. mpc8280 and MPC8270 (zu package) pinout list (continued) pin name ball mpc8280/MPC8270 mpc8280 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 46 freescale semiconductor pinout d37 c8 d38 e7 d39 a3 d40 d18 d41 a17 d42 a14 d43 b12 d44 a10 d45 d8 d46 b6 d47 c4 d48 c18 d49 e16 d50 b14 d51 c12 d52 b10 d53 a7 d54 c6 d55 d5 d56 b18 d57 b16 d58 e14 d59 d12 d60 c10 d61 e8 d62 d6 d63 c2 dp0/rsrv /ext_br2 b22 irq1 /dp1/ext_bg2 a22 irq2 /dp2/tlbisync /ext_dbg2 e21 irq3 /dp3/ckstp_out /ext_br3 d21 irq4 /dp4/core_sreset /ext_bg3 c21 irq5 /cint /dp5/tben /ext_dbg3 b21 table 20. mpc8280 and MPC8270 (zu package) pinout list (continued) pin name ball mpc8280/MPC8270 mpc8280 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 47 pinout irq6 /dp6/cse0 a21 irq7 /dp7/cse1 e20 psdval v3 ta c22 tea v5 gbl /irq1 w1 ci /baddr29/irq2 u2 wt /baddr30/irq3 u3 l2_hit /irq4 y4 cpu_bg /baddr31/irq5 /cint u4 cpu_dbg r2 cpu_br y3 cs0 f25 cs1 c29 cs2 e27 cs3 e28 cs4 f26 cs5 f27 cs6 f28 cs7 g25 cs8 d29 cs9 e29 cs10 /bctl1 f29 cs11 /ap0 g28 baddr27 t5 baddr28 u1 ale t2 bctl0 a27 pwe0 /psddqm0 /pbs0 c25 pwe1 /psddqm1 /pbs1 e24 pwe2 /psddqm2 /pbs2 d24 pwe3 /psddqm3 /pbs3 c24 pwe4 /psddqm4 /pbs4 b26 table 20. mpc8280 and MPC8270 (zu package) pinout list (continued) pin name ball mpc8280/MPC8270 mpc8280 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 48 freescale semiconductor pinout pwe5 /psddqm5 /pbs5 a26 pwe6 /psddqm6 /pbs6 b25 pwe7 /psddqm7 /pbs7 a25 psda10/pgpl0 e23 psdwe /pgpl1 b24 poe /psdras /pgpl2 a24 psdcas /pgpl3 b23 pgta /pupmwait/pgpl4/ppbs a23 psdamux/pgpl5 d22 lwe0 /lsddqm0 /lbs0 /pci_cfg0 h28 lwe1 /lsddqm1 /lbs1 /pci_cfg1 h27 lwe2 /lsddqm2 /lbs2 /pci_cfg2 h26 lwe3 /lsddqm3 /lbs3 /pci_cfg3 g29 lsda10/lgpl0/pci_modckh0 d27 lsdwe /lgpl1/pci_modckh1 c28 loe /lsdras /lgpl2/pci_modckh2 e26 lsdcas /lgpl3/pci_modckh3 d25 lgta /lupmwait/lgpl4/lpbs c26 lgpl5/lsdamux/pci_modck b27 lwr d28 l_a14/par n27 l_a15/frame /smi t29 l_a16/trdy r27 l_a17/irdy /ckstp_out r26 l_a18/stop r29 l_a19/devsel r28 l_a20/idsel w29 l_a21/perr p28 l_a22/serr n26 l_a23/req0 aa27 l_a24/req1 /hsejsw p29 l_a25/gnt0 aa26 l_a26/gnt1 /hsled n25 table 20. mpc8280 and MPC8270 (zu package) pinout list (continued) pin name ball mpc8280/MPC8270 mpc8280 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 49 pinout l_a27/gnt2 /hsenum aa25 l_a28/rst /core_sreset ab29 l_a29/inta ab28 l_a30/req2 p25 l_a31/dllout ab27 lcl_d0/ad0 h29 lcl_d1/ad1 j29 lcl_d2/ad2 j28 lcl_d3/ad3 j27 lcl_d4/ad4 j26 lcl_d5/ad5 j25 lcl_d6/ad6 k25 lcl_d7/ad7 l29 lcl_d8/ad8 l27 lcl_d9/ad9 l26 lcl_d10/ad10 l25 lcl_d11/ad11 m29 lcl_d12/ad12 m28 lcl_d13/ad13 m27 lcl_d14/ad14 m26 lcl_d15/ad15 n29 lcl_d16/ad16 t25 lcl_d17/ad17 u27 lcl_d18/ad18 u26 lcl_d19/ad19 u25 lcl_d20/ad20 v29 lcl_d21/ad21 v28 lcl_d22/ad22 v27 lcl_d23/ad23 v26 lcl_d24/ad24 w27 lcl_d25/ad25 w26 lcl_d26/ad26 w25 lcl_d27/ad27 y29 table 20. mpc8280 and MPC8270 (zu package) pinout list (continued) pin name ball mpc8280/MPC8270 mpc8280 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 50 freescale semiconductor pinout lcl_d28/ad28 y28 lcl_d29/ad29 y25 lcl_d30/ad30 aa29 lcl_d31/ad31 aa28 lcl_dp0/c0/be0 l28 lcl_dp1/c1/be1 n28 lcl_dp2/c2/be2 t28 lcl_dp3/c3/be3 w28 irq0 /nmi_out t1 irq7 /int_out /ape d1 trst 1 ah3 tck ag5 tms aj3 tdi ae6 tdo af5 tris ab4 poreset 1 ag6 hreset ah5 sreset af6 qreq aa3 rstconf aj4 modck1/ap1/tc0/bnksel0 w2 modck2/ap2/tc1/bnksel1 w3 modck3/ap3/tc2/bnksel2 w4 clkin1 ah4 pa0/restart1 /dreq3 fcc2_utm_txaddr2 ac29 2 pa1/reject1 /done3 fcc2_utm_txaddr1 ac25 2 pa2/clk20/dack3 fcc2_utm_txaddr0 ae28 2 pa3/clk19/dack4 /l1rxd1a2 fcc2_utm_rxaddr0 ag29 2 pa4/reject2 /done4 fcc2_utm_rxaddr1 ag28 2 pa5/restart2 /dreq4 fcc2_utm_rxaddr2/fcc1_ut_rx prty ag26 2 pa6/fcc2_rxaddr3 l1rsynca1 ae24 2 pa7/smsyn2/fcc2_txaddr3 l1tsynca1/l1gnta1 ah25 2 table 20. mpc8280 and MPC8270 (zu package) pinout list (continued) pin name ball mpc8280/MPC8270 mpc8280 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 51 pinout pa8/smrxd2/fcc2_txaddr4 l1rxd0a1/l1rxda1 af23 2 pa9/smtxd2 l1txd0a1 ah23 2 pa10/msnum5 fcc1_ut8_rxd0/fcc1_ut16_rxd8 ae22 2 pa11/msnum4 fcc1_ut8_rxd1/fcc1_ut16_rxd9 ah22 2 pa12/msnum3 fcc1_ut8_rxd2/ fcc1_ut16_rxd10 aj21 2 pa13/msnum2 fcc1_ut8_rxd3/ fcc1_ut16_rxd11 ah20 2 pa14/fcc1_mii_hdlc_rxd3 fcc1_ut8_rxd4/ fcc1_ut16_rxd12 ag19 2 pa15/fcc1_mii_hdlc_rxd2 fcc1_ut8_rxd5/ fcc1_ut16_rxd13 af18 2 pa16/fcc1_mii_hdlc_rxd1/ fcci_rmii_rxd1 fcc1_ut8_rxd6/ fcc1_ut16_rxd14 af17 2 pa17/fcc1_mii_hdlc_rxd0/ fcc1_mii_tran_rxd/ fcci_rmii_rxd0 fcc1_ut8_rxd7/ fcc1_ut16_rxd15 ae16 2 pa18/fcc1_mii_hdlc_txd0/ fcc1_mii_tran_txd/ fcc1_rmii_txd0 fcc1_ut8_txd7/fcc1_ut16_txd15 aj16 2 pa19/fcc1_mii_hdlc_txd1/ fcc1_rmii_txd1 fcc1_ut8_txd6/fcc1_ut16_txd14 ag15 2 pa20/fcc1_mii_hdlc_txd2 fcc1_ut8_txd5/fcc1_ut16_txd13 aj13 2 pa21/fcc1_mii_hdlc_txd3 fcc1_ut8_txd4/fcc1_ut16_txd12 ae13 2 pa22 fcc1_ut8_txd3/fcc1_ut16_txd11 af12 2 pa23 fcc1_ut8_txd2/fcc1_ut16_txd10 ag11 2 pa24/msnum1 fcc1_ut8_txd1/fcc1_ut16_txd9 ah9 2 pa25/msnum0 fcc1_ut8_txd0/fcc1_ut16_txd8 aj8 2 pa26/fcc1_rmii_rx_er fcc1_utm_rxclav/ fcc1_uts_rxclav ah7 2 pa27/fcc1_mii_rx_dv/ fcc1_rmii_crs_dv fcc1_ut_rxsoc af7 2 pa28/fcc1_mii_tx_en/ fcc1_rmii_tx_en fcc1_utm_rxenb / fcc1_uts_rxenb ad5 2 pa29/fcc1_mii_tx_er fcc1_ut_txsoc af1 2 pa30/fcc1_mii_crs/fcc1_rts fcc1_utm_txclav/ fcc1_uts_txclav ad3 2 pa31/fcc1_mii_col fcc1_utm_txenb / fcc1_uts_txenb ab5 2 table 20. mpc8280 and MPC8270 (zu package) pinout list (continued) pin name ball mpc8280/MPC8270 mpc8280 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 52 freescale semiconductor pinout pb4/fcc3_mii_hdlc_txd3/ l1rsynca2/fcc3_rts fcc2_ut8_rxd0 ad28 2 pb5/fcc3_mii_hdlc_txd2/ l1tsynca2/l1gnta2 fcc2_ut8_rxd1 ad26 2 pb6/fcc3_mii_hdlc_txd1/ fcc3_rmii_txd1/ l1rxda2/l1rxd0a2 fcc2_ut8_rxd2 ad25 2 pb7/fcc3_mii_hdlc_txd0/ fcc3_rmii_txd0/ fcc3_txd/l1txda2/l1txd0a2 fcc2_ut8_rxd3 ae26 2 pb8/fcc3_mii_hdlc_rxd0/ fcc3_rmii_rxd0/ fcc3_rxd/txd3 fcc2_ut8_txd3/l1rsyncd1 ah27 2 pb9/fcc3_mii_hdlc_rxd1/ fcc3_rmii_rxd1/l1txd2a2 fcc2_ut8_txd2/l1tsyncd1/ l1gntd1 ag24 2 pb10/fcc3_mii_hdlc_rxd2 fcc2_ut8_txd1/l1rxdd1 ah24 2 pb11/fcc3_mii_hdlc_rxd3 fcc2_ut8_txd0/l1txdd1 aj24 2 pb12/fcc3_mii_crs/txd2 l1clkob1/l1rsyncc1 ag22 2 pb13/fcc3_mii_col/l1txd1a2 l1rqb1 /l1tsyncc1/l1gntc1 ah21 2 pb14/fcc3_mii_rmii_tx_en//rxd3 l1rxdc1 ag20 2 pb15/fcc3_mii_tx_er/rxd2 l1txdc1 af19 2 pb16/fcc3_mii_rmii_rx_er/clk18 l1clkoa1 aj18 2 pb17/fcc3_mii_rx_dv/clk17/ fcc3_rmii_crs_dv l1rqa1 aj17 2 pb18/fcc2_mii_hdlc_rxd3/ l1clkod2/l1rxd2a2 fcc2_ut8_rxd4 ae14 2 pb19fcc2_mii_hdlc_rxd2/ l1rqd2/l1rxd3a2 fcc2_ut8_rxd5 af13 2 pb20/fcc2_mii_hdlc_rmii_rxd1/ l1rsyncd2 fcc2_ut8_rxd6/l1txd1a1 ag12 2 pb21//fcc2_mii_hdlc_rmii_rxd0/ fcc2_tran_rxd/l1tsyncd2/ l1gntd2 fcc2_ut8_rxd7/l1txd2a1 ah11 2 pb22/fcc2_mii_hdlc_txd0/ fcc2_txd/fcc2_rmii_txd0/ l1rxdd2 fcc2_ut8_txd7/l1rxd1a1 ah16 2 pb23/fcc2_mii_hdlc_txd1/ l1rxd2a1/l1txdd2/ fcc2_rmii_txd1 fcc2_ut8_txd6/l1rxd2a1 ae15 2 pb24/fcc2_mii_hdlc_txd2/ l1rsyncc2 fcc2_ut8_txd5/l1rxd3a1 aj9 2 table 20. mpc8280 and MPC8270 (zu package) pinout list (continued) pin name ball mpc8280/MPC8270 mpc8280 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 53 pinout pb25/fcc2_mii_hdlc_txd3/ l1tsyncc2/l1gntc2 fcc2_ut8_txd4/l1txd3a1 ae9 2 pb26/fcc2_mii_crs/l1rxdc2 fcc2_ut8_txd1 aj7 2 pb27/fcc2_mii_col/l1txdc2 fcc2_ut8_txd0 ah6 2 pb28/fcc2_mii_rx_er/ fcc2_rmii_rx_er/fcc2_rts / l1tsyncb2/l1gntb2/txd1 ae3 2 pb29/l1rsyncb2/fcc2_mii_tx_en/ fcc2_rmii_tx_en fcc2_utm_rxclav/ fcc2_uts_rxclav ae2 2 pb30/fcc2_mii_rx_dv/ fcc2_rmii_crs_dv/l1rxdb2 fcc2_ut_txsoc ac5 2 pb31/fcc2_mii_tx_er/l1txdb2 fcc2_ut_rxsoc ac4 2 pc0/dreq1/brgo7/smsyn2 / l1clkoa2 ab26 2 pc1/dreq2/brgo6/l1rqa2 / spisel ad29 2 pc2/fcc3_cd /done2 fcc2_ut8_txd3 ae29 2 pc3/fcc3_cts /dack2 /cts4/ usb_rp fcc2_ut8_txd2 ae27 2 pc4/si2_l1st4/fcc2_cd fcc2_utm_rxenb / fcc2_uts_rxenb af27 2 pc5/si2_l1st3/fcc2_cts fcc2_utm_txclav/ fcc2_uts_txclav af24 2 pc6/fcc1_cd l1clkoc1/fcc1_utm_rxaddr2/ fcc1_uts_rxaddr2/ fcc1_utm_rxclav1 aj26 2 pc7/fcc1_cts l1rqc1 /fcc1_utm_txaddr2/ fcc1_uts_txaddr2/ fcc1_utm_txclav1 aj25 2 pc8/cd4 /rena4/si2_l1st2/cts3 / usbrn fcc1_ut16_txd0 af22 2 pc9/cts4 /clsn4/si2_l1st1/ l1tsynca2/l1gnta2/usb_rp fcc1_ut16_txd1 ae21 2 pc10/cd3 /rena3 fcc1_ut16_txd2/si1_l1st4/ fcc2_ut8_rxd3 af20 2 pc11/cts3 /clsn3/l1txd3a2 l1clkod1/fcc2_ut8_rxd2 ae19 2 pc12/cd2 /rena2 si1_l1st3/fcc1_utm_rxaddr1/ fcc1_uts_rxaddr1 ae18 2 pc13/cts2 /clsn2 l1rqd1 /fcc1_utm_txaddr1/ fcc1_uts_txaddr1 ah18 2 table 20. mpc8280 and MPC8270 (zu package) pinout list (continued) pin name ball mpc8280/MPC8270 mpc8280 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 54 freescale semiconductor pinout pc14/cd1 /rena1 fcc1_utm_rxaddr0/ fcc1_uts_rxaddr0 ah17 2 pc15/cts1 /clsn1/smtxd2 fcc1_utm_txaddr0/ fcc1_uts_txaddr0 ag16 2 pc16/clk16/tin4 af15 2 pc17/clk15/tin3/brgo8 aj15 2 pc18/clk14/tgate2 ah14 2 pc19/clk13/brgo7/spiclk ag13 2 pc20/clk12/tgate1 /usb_oe ah12 2 pc21/clk11/brgo6 aj11 2 pc22/clk10/done1 /fcc1_ut_txprty ag10 2 pc23/clk9/brgo5/dack1 ae10 2 pc24/clk8/tout4 fcc2_ut8_txd3 af9 2 pc25/clk7/brgo4 fcc2_ut8_txd2 ae8 2 pc26/clk6/tout3 /tmclk aj6 2 pc27/fcc3_txd/fcc3_mii_txd0/ fcc3_rmii_txd0/clk5/brgo3 ag2 2 pc28/clk4/tin1/tout2 /cts2 /clsn2/ fcc2_rxaddr4 af3 2 pc29/clk3/tin2/brgo2/cts1 /clsn1 af2 2 pc30/clk2/tout1 fcc2_ut8_txd3 ae1 2 pc31/clk1/brgo1 ad1 2 pd4/brgo8/fcc3_rts /smrxd2 l1tsyncd1/l1gntd1 ac28 2 pd5/done1 fcc1_ut16_txd3 ad27 2 pd6/dack1 fcc1_ut16_txd4 af29 2 pd7/smsyn1/fcc1_txclav2 fcc1_utm_txaddr3/ fcc1_uts_txaddr3/ fcc2_utm_txaddr4 fcc2_uts_txaddr1 af28 2 pd8/smrxd1/brgo5 fcc2_ut_txprty ag25 2 pd9/smtxd1/brgo3 fcc2_ut_rxprty ah26 2 pd10/l1clkob2/brgo4 fcc2_ut8_rxd1/l1rsyncb1 aj27 2 pd11/l1rqb2 fcc2_ut8_rxd0/l1tsyncb1/ l1gntb1 aj23 2 pd12 si1_l1st2/l1rxdb1 ag23 2 pd13 si1_l1st1/l1txdb1 aj22 2 table 20. mpc8280 and MPC8270 (zu package) pinout list (continued) pin name ball mpc8280/MPC8270 mpc8280 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 55 pinout pd14/l1clkoc2/i2cscl fcc1_ut16_rxd0 ae20 2 pd15/l1rqc2 /i2csda fcc1_ut16_rxd1 aj20 2 pd16/spimiso fcc1_ut_txprty/l1tsyncc1/ l1gntc1 ag18 2 pd17/brgo2/spimosi fcc1_ut_rxprty ag17 2 pd18/spiclk fcc1_utm_rxaddr4/ fcc1_uts_rxaddr4/ fcc1_utm_rxclav3/ fcc2_utm_rxaddr3/ fcc2_uts_rxaddr0 af16 2 pd19/spisel/brgo1 fcc1_utm_txaddr4/ fcc1_uts_txaddr4/ fcc1_utm_txclav3/ fcc2_utm_txaddr3/ fcc2_uts_txaddr0 ah15 2 pd20/rts4 /tena4/l1rsynca2/ usb_tp fcc1_ut16_rxd2 aj14 2 pd21/txd4/l1rxd0a2/l1rxda2/ usb_tn fcc1_ut16_rxd3 ah13 2 pd22/rxd4l1txd0a2/l1txda2/ usb_rxd fcc1_ut16_txd5 aj12 2 pd23/rts3 /tena3 fcc1_ut16_rxd4/l1rsyncd1 ae12 2 pd24/txd3 fcc1_ut16_rxd5/l1rxdd1 af10 2 pd25/rxd3 fcc1_ut16_txd6/l1txdd1 ag9 2 pd26/rts2 /tena2 fcc1_ut16_rxd6/l1rsyncc1 ah8 2 pd27/txd2 fcc1_ut16_rxd7/l1rxdc1 ag7 2 pd28/rxd2 fcc1_ut16_txd7/l1txdc1 ae4 2 pd29/rts1 /tena1 fcc1_utm_rxaddr3/ fcc1_uts_rxaddr3/ fcc1_utm_rxclav2/ fcc2_utm_rxaddr4/ fcc2_uts_rxaddr1 ag1 2 pd30/txd1 fcc2_utm_txenb / fcc2_uts_txenb ad4 2 pd31/rxd1 ad2 2 vccsyn ab3 vccsyn1 b9 clkin2 ae11 spare4 3 u5 table 20. mpc8280 and MPC8270 (zu package) pinout list (continued) pin name ball mpc8280/MPC8270 mpc8280 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 56 freescale semiconductor pinout symbols used in table 20 are described in table 21 . pci_mode 4 af25 spare6 3 v4 no connect 5 aa1, ag4 i/o power ag21, ag14, ag8, aj1, aj2, ah1, ah2, ag3, af4, ae5, ac27, y27, t27, p27, k26, g27, ae25, af26, ag27, ah28, ah29, aj28, aj29, c7, c14, c16, c20, c23, e10, a28, a29, b28, b29, c27, d26, e25, h3, m4, t3, aa4, a1, a2, b1, b2, c3, d4, e5 core power u28, u29, k28, k29, a9, a19, b19, m1, m2, y1, y2, ac1, ac2, ah19, aj19, ah10, aj10, aj5 ground aa5, ab1 6 , ab2 7 , af21, af14, af8, ae7, af11, ae17, ae23, ac26, ab25, y26, v25, t26, r25, p26, m25, k27, h25, g26, d7, d10, d14, d16, d20, d23, c9, e11, e13, e15, e19, e22, b3, g5, h4, k5, m3, p5, t4, y5, aa2, ac3 1 should be tied to vddh via a 2k ? external pull-up resistor. 2 the default configuration of the cpm pins (pa[0?31], pb[4?31], pc[0?31], pd[4?31]) is input. to prevent excessive dc current, it is recommended to either pull unused pins to gnd or vddh, or to configure them as outputs. 3 must be pulled down or left floating. 4 if pci is not desired, must be pulled up or left floating. 5 sphere is not connected to die. 6 gndsyn (ab1): this pin exists as a separate ground signal in mpc826x(a) devices; it does not exist as a separate ground signal on the mpc8280. new designs must connect ab1 to gnd and follow the suggestions in section 4.6, ?layout practices .? old designs in which the mpc8280 is used as a drop-in replacement can leave the pin connected to gnd with the noise filtering capacitors. 7 xfc (ab2) pin: this pin is used in mpc826x(a) devices; it is not used in mpc8280 because there is no need for external capacitor to operate the pll. new designs should connect ab2 (xfc) pin to gnd. old designs in which the mpc8280 is used as a drop-in replacement can leave the pin connected to the current capacitor. table 21. symbol legend symbol meaning overbar signals with overbars, such as ta , are active low. utm indicates that a signal is part of the utopia master interface. uts indicates that a signal is part of the utopia slave interface. table 20. mpc8280 and MPC8270 (zu package) pinout list (continued) pin name ball mpc8280/MPC8270 mpc8280 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 57 pinout 8.2 vr and zq packages?mpc8275 and MPC8270 the following figures and table represent the alternate 516 pbga package. for information on the standard package for the mpc8280 and the MPC8270, refer to section 8.1, ?zu package?mpc8280 and MPC8270? on page 42. figure 15 shows the pinout of the vr and zq packages as viewed from the top surface. figure 15. pinout of the 516 pbga package (view from top) ut8 indicates that a signal is part of the 8-bit utopia interface. ut16 indicates that a signal is part of the 16-bit utopia interface. mii indicates that a signal is part of the media independent interface. rmii indicates that a signal is part of the reduced media independent interface. table 21. symbol legend (continued) symbol meaning 12345678910111213141516 17 18 19 20 21 22 23 24 25 26 not to scale 1234567891011121314151617181920212223242526 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 58 freescale semiconductor pinout figure 16 shows the side profile of the pbga package to indicate the direction of the top surface view. figure 16. side view of the pbga package remove note: temperature reflow for the vr package in the vr package, sphere composition is lead-free (refer to ta ble 2 ). this requires higher temperature reflow than what is required for other powerquicc ii packages. users should consult ?freescale powerquicc ii? pb-free packaging information? (mpc8250pbfreepkg) available at www.freescale.com. table 22 shows the pinout list of the mpc8275 and MPC8270. table 21 defines conventions and acronyms used in table 22 . table 22. mpc8275 and MPC8270 (vr and zq packages) pinout list pin name ball mpc8275/MPC8270 mpc8275 only br c16 bg d2 abb /irq2 c1 ts d1 a0 d5 a1 e8 a2 c4 a3 b4 a4 a4 a5 d7 a6 d8 a7 c6 a8 b5 a9 b6 a10 c7 die transfer molding compound 1 mm pitch wire bonds attach die ball bond screen-printed solder mask cu substrate traces bt resin glass epoxy plated substrate via
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 59 pinout a11 c8 a12 a6 a13 d9 a14 f11 a15 b7 a16 b8 a17 c9 a18 a7 a19 b9 a20 e11 a21 a8 a22 d11 a23 b10 a24 c11 a25 a9 a26 b11 a27 c12 a28 d12 a29 a10 a30 b12 a31 b13 tt0 e7 tt1 b3 tt2 f8 tt3 a3 tt4 c3 tbst f5 tsiz0 e3 tsiz1 e2 tsiz2 e1 tsiz3 e4 aack d3 artry c2 table 22. mpc8275 and MPC8270 (vr and zq packages) pinout list (continued) pin name ball mpc8275/MPC8270 mpc8275 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 60 freescale semiconductor pinout dbg a14 dbb /irq3 c15 d0 w4 d1 y1 d2 v1 d3 p4 d4 n3 d5 k5 d6 j4 d7 g1 d8 ab1 d9 u4 d10 u2 d11 n6 d12 n1 d13 l1 d14 j5 d15 g3 d16 aa2 d17 w1 d18 t3 d19 t1 d20 m2 d21 k2 d22 j1 d23 g4 d24 u5 d25 t5 d26 p5 d27 p3 d28 m3 d29 k3 d30 h2 table 22. mpc8275 and MPC8270 (vr and zq packages) pinout list (continued) pin name ball mpc8275/MPC8270 mpc8275 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 61 pinout d31 g5 d32 aa1 d33 v2 d34 u1 d35 p2 d36 m4 d37 k4 d38 h3 d39 f2 d40 y2 d41 u3 d42 t2 d43 n2 d44 m5 d45 k1 d46 h4 d47 f1 d48 w2 d49 t4 d50 r3 d51 n4 d52 m1 d53 j2 d54 h5 d55 f3 d56 v3 d57 r5 d58 r2 d59 n5 d60 l2 d61 j3 d62 h1 d63 f4 table 22. mpc8275 and MPC8270 (vr and zq packages) pinout list (continued) pin name ball mpc8275/MPC8270 mpc8275 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 62 freescale semiconductor pinout dp0/rsrv /ext_br2 ab3 irq1 /dp1/ext_bg2 w5 irq2 /dp2/tlbisync /ext_dbg2 ac2 irq3 /dp3/ckstp_out /ext_br3 aa3 irq4 /dp4/core_sreset /ext_bg3 ad1 irq5 /cint /dp5/tben /ext_dbg3 ac1 irq6 /dp6/cse0 ab2 irq7 /dp7/cse1 y3 psdval d15 ta y4 tea d16 gbl /irq1 e15 ci /baddr29/irq2 d14 wt /baddr30/irq3 e14 l2_hit /irq4 a17 cpu_bg /baddr31/irq5 /cint b14 cpu_dbg f13 cpu_br b17 cs0 ac6 cs1 ad6 cs2 ae6 cs3 ab7 cs4 af7 cs5 ac7 cs6 ad7 cs7 af8 cs8 ae8 cs9 ad8 cs10 /bctl1 ac8 cs11 /ap0 ab8 baddr27 c13 baddr28 a12 ale d13 table 22. mpc8275 and MPC8270 (vr and zq packages) pinout list (continued) pin name ball mpc8275/MPC8270 mpc8275 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 63 pinout bctl0 af4 pwe0 /psddqm0 /pbs0 aa5 pwe1 /psddqm1 /pbs1 ae4 pwe2 /psddqm2 /pbs2 ad4 pwe3 /psddqm3 /pbs3 af3 pwe4 /psddqm4 /pbs4 ab4 pwe5 /psddqm5 /pbs5 ae3 pwe6 /psddqm6 /pbs6 af2 pwe7 /psddqm7 /pbs7 ad3 psda10/pgpl0 ae2 psdwe /pgpl1 ad2 poe /psdras /pgpl2 ae1 psdcas /pgpl3 ac3 pgta /pupmwait/pgpl4/ppbs w6 psdamux/pgpl5 aa4 lwe0 /lsddqm0 /lbs0 /pci_cfg0 ac9 lwe1 /lsddqm1 /lbs1 /pci_cfg1 ad9 lwe2 /lsddqm2 /lbs2 /pci_cfg2 ae9 lwe3 /lsddqm3 /lbs3 /pci_cfg3 af9 lsda10/lgpl0/pci_modckh0 ab6 lsdwe /lgpl1/pci_modckh1 af5 loe /lsdras /lgpl2/pci_modckh2 ae5 lsdcas /lgpl3/pci_modckh3 ad5 lgta /lupmwait/lgpl4/lpbs ac5 lgpl5/lsdamux/pci_modck ab5 lwr af6 l_a14/par ae13 l_a15/frame /smi ad15 l_a16/trdy af16 l_a17/irdy /ckstp_out af15 l_a18/stop ae15 l_a19/devsel ae14 l_a20/idsel ac17 table 22. mpc8275 and MPC8270 (vr and zq packages) pinout list (continued) pin name ball mpc8275/MPC8270 mpc8275 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 64 freescale semiconductor pinout l_a21/perr ad14 l_a22/serr af13 l_a23/req0 ae20 l_a24/req1 /hsejsw ac14 l_a25/gnt0 ac19 l_a26/gnt1 /hsled ad13 l_a27/gnt2 /hsenum af21 l_a28/rst /core_sreset af22 l_a29/inta ae21 l_a30/req2 ab14 l_a31/dllout ad20 lcl_d0/ad0 ab9 lcl_d1/ad1 ab10 lcl_d2/ad2 ac10 lcl_d3/ad3 ad10 lcl_d4/ad4 ae10 lcl_d5/ad5 af10 lcl_d6/ad6 af11 lcl_d7/ad7 ab12 lcl_d8/ad8 ab11 lcl_d9/ad9 af12 lcl_d10/ad10 ae11 lcl_d11/ad11 ac13 lcl_d12/ad12 ac12 lcl_d13/ad13 ab13 lcl_d14/ad14 ad12 lcl_d15/ad15 af14 lcl_d16/ad16 af17 lcl_d17/ad17 ae16 lcl_d18/ad18 ad16 lcl_d19/ad19 ac16 lcl_d20/ad20 ab16 lcl_d21/ad21 af18 table 22. mpc8275 and MPC8270 (vr and zq packages) pinout list (continued) pin name ball mpc8275/MPC8270 mpc8275 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 65 pinout lcl_d22/ad22 ae17 lcl_d23/ad23 ad17 lcl_d24/ad24 ab17 lcl_d25/ad25 ae18 lcl_d26/ad26 ad18 lcl_d27/ad27 ac18 lcl_d28/ad28 ae19 lcl_d29/ad29 af20 lcl_d30/ad30 ad19 lcl_d31/ad31 ab18 lcl_dp0/c0/be0 ae12 lcl_dp1/c1/be1 aa13 lcl_dp2/c2/be2 ac15 lcl_dp3/c3/be3 af19 irq0 /nmi_out a11 irq7 /int_out /ape e5 trst 1 f22 tck a24 tms c24 tdi a25 tdo b24 tris c19 poreset 1 b25 hreset d24 sreset e23 qreq d18 rstconf e24 modck1/ap1/tc0/bnksel0 b16 modck2/ap2/tc1/bnksel1 f16 modck3/ap3/tc2/bnksel2 a15 clkin1 g22 pa0/restart1 /dreq3 fcc2_utm_txaddr2 ac20 2 pa1/reject1 /done3 fcc2_utm_txaddr1 ac21 2 table 22. mpc8275 and MPC8270 (vr and zq packages) pinout list (continued) pin name ball mpc8275/MPC8270 mpc8275 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 66 freescale semiconductor pinout pa2/clk20/dack3 fcc2_utm_txaddr0 af25 2 pa3/clk19/dack4 /l1rxd1a2 fcc2_utm_rxaddr0 ae24 2 pa4/reject2 /done4 fcc2_utm_rxaddr1 aa21 2 pa5/restart2 /dreq4 fcc2_utm_rxaddr2 ad25 2 pa6 fcc2_ut_rxaddr3 ac24 2 pa7/smsyn2 fcc2_ut_txaddr3 aa22 2 pa8/smrxd2 fcc2_ut_txaddr4 aa23 2 pa 9/ s m t x d 2 y26 2 pa10/msnum5 fcc1_ut8_rxd0/fcc1_ut16_rxd8 w22 2 pa11/msnum4 fcc1_ut8_rxd1/fcc1_ut16_rxd9 w23 2 pa12/msnum3 fcc1_ut8_rxd2/ fcc1_ut16_rxd10 v26 2 pa13/msnum2 fcc1_ut8_rxd3/ fcc1_ut16_rxd11 v25 2 pa14/fcc1_mii_hdlc_rxd3 fcc1_ut8_rxd4/ fcc1_ut16_rxd12 t22 2 pa15/fcc1_mii_hdlc_rxd2 /fcc1_ut8_rxd5/ fcc1_ut16_rxd13 t25 2 pa16/fcc1_mii_hdlc_rxd1/ fcc1_rmii_rxd1 fcc1_ut8_rxd6/ fcc1_ut16_rxd14 r24 2 pa17/fcc_mii_hdlc_rxd0/ fcc1_mii_tran_rxd/ fcci_rmii_rxd0 fcc1_ut8_rxd7/ fcc1_ut16_rxd15 p22 2 pa18/fcc1_mii_hdlc_txd0/ fcc1_miitran_txd/ fcc1_rmii_txd0 fcc1_ut8_txd7/fcc1_ut16_txd15 n26 2 pa19/fcc1_mii_hdlc_txd1/ fcc1_rmii_txd1 fcc1_ut8_txd6/fcc1_ut16_txd14 n23 2 pa20/fcc1_mii_hdlc_txd2 fcc1_ut8_txd5/fcc1_ut16_txd13 k26 2 pa21/fcc1_mii_hdlc_txd3 fcc1_ut8_txd4/fcc1_ut16_txd12 l23 2 pa22 fcc1_ut8_txd3/fcc1_ut16_txd11 k23 2 pa23 fcc1_ut8_txd2/fcc1_ut16_txd10 h26 2 pa24/msnum1 fcc1_ut8_txd1/fcc1_ut16_txd9 f25 2 pa25/msnum0 fcc1_ut8_txd0/fcc1_ut16_txd8 d26 2 pa26/fcc1_mii_rmii_rx_er/ fcc1_utm_rxclav/ fcc1_uts_rxclav d25 2 pa27/fcc1_mii_rx_dv/ fcc1_rmii_crs_dv fcc1_ut_rxsoc c25 2 table 22. mpc8275 and MPC8270 (vr and zq packages) pinout list (continued) pin name ball mpc8275/MPC8270 mpc8275 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 67 pinout pa28/fcc1_mii_tx_en/ fcc1_rmii_tx_en fcc1_utm_rxenb / fcc1_uts_rxenb c22 2 pa29/fcc1_mii_tx_er fcc1_ut_txsoc b21 2 pa30/fcc1_mii_crs/fcc1_rts fcc1_utm_txclav/ fcc1_uts_txclav a20 2 pa31/fcc1_mii_col fcc1_utm_txenb / fcc1_uts_txenb a19 2 pb4/fcc3_mii_hdlc_txd3/ l1rsynca2/fcc3_rts fcc2_ut8_rxd0 ad21 2 pb5/fcc3_mii_hdlc_txd2/ l1tsynca2/l1gnta2 fcc2_ut8_rxd1 ad22 2 pb6/fcc3_mii_hdlc_txd1/ fcc3_rmii_txd1/ l1rxda2/l1rxd0a2 fcc2_ut8_rxd2 ac22 2 pb7/fcc3_mii_hdlc_txd0/ fcc3_rmii_txd0/ fcc3_txd/l1txda2/l1txd0a2 fcc2_ut8_rxd3 ae26 2 pb8/fcc3_mii_hdlc_rxd0/ fcc3_rmii_rxd0/ fcc3_rxd/txd3 fcc2_ut8_txd3 ab23 2 pb9/fcc3_mii_hdlc_rxd1/ fcc3_rmii_rxd1/l1txd2a2 fcc2_ut8_txd2 ac26 2 pb10/fcc3_mii_hdlc_rxd2 fcc2_ut8_txd1 ab26 2 pb11/fcc3_mii_hdlc_rxd3 fcc2_ut8_txd0 aa25 2 pb12/fcc3_mii_crs/txd2 w26 2 pb13/fcc3_mii_col/l1txd1a2 w25 2 pb14/fcc3_mii_rmii_tx_en/rxd3 v24 2 pb15/fcc3_mii_tx_er/rxd2 u24 2 pb16/fcc3_mii_rmii_rx_er/clk18 r22 2 pb17/fcc3_mii_rx_dv/clk17/ fcc3_rmii_crs_dv r23 2 pb18/fcc2_mii_hdlc_rxd3/ l1clkod2/l1rxd2a2 fcc2_ut8_rxd4 m23 2 pb19fcc2_mii_hdlc_rxd2/ l1rqd2/l1rxd3a2 fcc2_ut8_rxd5 l24 2 pb20/fcc2_mii_hdlc_rmii_rxd1/ l1rsyncd2 fcc2_ut8_rxd6 k24 2 pb21//fcc2_mii_hdlc_rmii_rxd0/ fcc2_tran_rxd/l1tsyncd2/ l1gntd2 fcc2_ut8_rxd7 l21 2 table 22. mpc8275 and MPC8270 (vr and zq packages) pinout list (continued) pin name ball mpc8275/MPC8270 mpc8275 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 68 freescale semiconductor pinout pb22/fcc2_mii_hdlc_rmii_txd0/ fcc2_txd/fcc2_rmii_txd0/ l1rxdd2 fcc2_ut8_txd7 p25 2 pb23/fcc2_mii_hdlc_txd1/ l1rxd2a1/l1txdd2/ fcc2_rmii_txd1 fcc2_ut8_txd6 n25 2 pb24/fcc2_mii_hdlc_txd2/ l1rsyncc2 fcc2_ut8_txd5 e26 2 pb25/fcc2_mii_hdlc_txd3/ l1tsyncc2/l1gntc2 fcc2_ut8_txd4 h23 2 pb26/fcc2_mii_crs/l1rxdc2 fcc2_ut8_txd1 c26 2 pb27/fcc2_mii_col/l1txdc2 fcc2_ut8_txd0 b26 2 pb28/fcc2_mii_rx_er/fcc2_rmii_rx_er/ fcc2_rts /l1tsyncb2/l1gntb2/txd1 a22 2 pb29/l1rsyncb2/ fcc2_mii_tx_en/fcc2_rmii_tx_en fcc2_utm_rxclav/ fcc2_uts_rxclav a21 2 pb30/fcc2_mii_rx_dv/l1rxdb2/ fcc2_rmii_crs_dv fcc2_ut_txsoc e20 2 pb31/fcc2_mii_tx_er/l1txdb2 fcc2_ut_rxsoc c20 2 pc0/dreq1/brgo7/smsyn2 / l1clkoa2 ae22 2 pc1/dreq2/spisel /brgo6/l1rqa2 aa19 2 pc2/fcc3_cd /done2 fcc2_ut8_txd3 af24 2 pc3/fcc3_cts /dack2 /cts4 / usb_rp fcc2_ut8_txd2 ae25 2 pc4/si2_l1st4/fcc2_cd fcc2_utm_rxenb / fcc2_uts_rxenb ab22 2 pc5/si2_l1st3/fcc2_cts fcc2_utm_txclav/ fcc2_uts_txclav ac25 2 pc6/fcc1_cd fcc1_utm_rxaddr2/ fcc1_uts_rxaddr2/ fcc1_utm_rxclav1 ab25 2 pc7/fcc1_cts fcc1_utm_txaddr2/ fcc1_uts_txaddr2/ fcc1_utm_txclav1 aa24 2 pc8/cd4 /rena4/si2_l1st2/cts3 / usb_rn fcc1_ut16_txd0 y24 2 pc9/cts4 /clsn4/si2_l1st1/ l1tsynca2/l1gnta2/usb_rp fcc1_ut16_txd1 u22 2 pc10/cd3 /rena3 fcc1_ut16_txd2/fcc2_ut8_rxd3 v23 2 table 22. mpc8275 and MPC8270 (vr and zq packages) pinout list (continued) pin name ball mpc8275/MPC8270 mpc8275 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 69 pinout pc11/cts3 /clsn3/l1txd3a2 fcc2_ut8_rxd2 u23 2 pc12/cd2 /rena2 fcc1_utm_rxaddr1/ fcc1_uts_rxaddr1 t26 2 pc13/cts2 /clsn2 fcc1_utm_txaddr1/ fcc1_uts_txaddr1 r26 2 pc14/cd1 /rena1 fcc1_utm_rxaddr0/ fcc1_uts_rxaddr0 p26 2 pc15/cts1 /clsn1/smtxd2 fcc1_utm_txaddr0/ fcc1_uts_txaddr0 p24 2 pc16/clk16/tin4 m26 2 pc17/clk15/tin3/brgo8 l26 2 pc18/clk14/tgate2 m24 2 pc19/clk13/brgo7/spiclk l22 2 pc20/clk12/tgate1 /usb_oe k25 2 pc21/clk11/brgo6 j25 2 pc22/clk10/done1 fcc1_ut_txprty g26 2 pc23/clk9/brgo5/dack1 f26 2 pc24/clk8/tout4 fcc2_ut8_txd3 g24 2 pc25/clk7/brgo4 fcc2_ut8_txd2 e25 2 pc26/clk6/tout3 /tmclk g23 2 pc27/fcc3_txd/fcc3_mii_txd0/ fcc3_rmii_txd0/clk5/brgo3 b23 2 pc28/clk4/tin1/tout2 /cts2 /clsn2 fcc2_ut_rxaddr4 e22 2 pc29/clk3/tin2/brgo2/cts1 /clsn1 e21 2 pc30/clk2/tout1 fcc2_ut8_txd3 d21 2 pc31/clk1/brgo1 b20 2 pd4/brgo8/fcc3_rts /smrxd2 af23 2 pd5/done1 fcc1_ut16_txd3 ae23 2 pd6/dack1 fcc1_ut16_txd4 ab21 2 pd7/smsyn1/fcc1_txclav2 fcc1_utm_txaddr3/ fcc1_uts_txaddr3/ fcc2_utm_txaddr4 fcc2_uts_txaddr1 ad23 2 pd8/smrxd1/brgo5 fcc2_ut_txprty ad26 2 pd9/smtxd1/brgo3 fcc2_ut_rxprty y22 2 pd10/l1clkob2/brgo4 fcc2_ut8_rxd1 ab24 2 table 22. mpc8275 and MPC8270 (vr and zq packages) pinout list (continued) pin name ball mpc8275/MPC8270 mpc8275 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 70 freescale semiconductor pinout pd11/l1rqb2 fcc2_ut8_rxd0 l1gntb1 y23 2 pd12 aa26 2 pd13 w24 2 pd14/l1clkoc2/i2cscl fcc1_ut16_rxd0 v22 2 pd15/l1rqc2 /i2csda fcc1_ut16_rxd1 u26 2 pd16/spimiso fcc1_ut_txprty t23 2 pd17/brgo2/spimosi fcc1_ut_rxprty r25 2 pd18/spiclk fcc1_utm_rxaddr4/ fcc1_uts_rxaddr4/ fcc1_utm_rxclav3/ fcc2_utm_rxaddr3/ fcc2_uts_rxaddr0 p23 2 pd19/spisel/brgo1 fcc1_utm_txaddr4/ fcc1_uts_txaddr4/ fcc1_utm_txclav3/ fcc2_utm_txaddr3/ fcc2_uts_txaddr0 n22 2 pd20/rts4 /tena4/l1rsynca2/ usb_tp fcc1_ut16_rxd2 m25 2 pd21/txd4/l1rxd0a2/l1rxda2/ usb_tn fcc1_ut16_rxd3 l25 2 pd22/rxd4l1txd0a2/l1txda2/ usb_rxd fcc1_ut16_txd5 j26 2 pd23/rts3 /tena3 fcc1_ut16_rxd4 k22 2 pd24/txd3 fcc1_ut16_rxd5 g25 2 pd25/rxd3 fcc1_ut16_txd6 h24 2 pd26/rts2 /tena2 fcc1_ut16_rxd6 f24 2 pd27/txd2 fcc1_ut16_rxd7 h22 2 pd28/rxd2 fcc1_ut16_txd7 b22 2 pd29/rts1 /tena1 fcc1_utm_rxaddr3/ fcc1_uts_rxaddr3/ fcc1_utm_rxclav2/ fcc2_utm_rxaddr4/ fcc2_uts_rxaddr1 d22 2 pd30/txd1 fcc2_utm_txenb / fcc2_uts_txenb c21 2 pd31/rxd1 e19 2 vccsyn d19 table 22. mpc8275 and MPC8270 (vr and zq packages) pinout list (continued) pin name ball mpc8275/MPC8270 mpc8275 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 71 pinout vccsyn1 k6 clkin2 k21 spare4 3 c14 pci_mode 4 ad24 spare6 3 b15 no connect 5 e17, c23 i/o power e6, f6, h6, l5, l6, p6, t6, u6, v5, y5, aa6, aa8, aa10, aa11, aa14, aa16, aa17, ab19, ab20, w21, u21, t21, p21, n21, m22, j22, h21, f21, f19, f17, e16, f14, e13, e12, f10, e10, e9 core power l3, v4, w3, ac11, ad11, ab15, u25, t24, j24, h25, f23, b19, d17, c17, d10, c10 ground b18 6 , a18 7 , a2, b1, b2, a5, c5, c18, d4, d6, g2, l4, p1, r1, r4, ac4, ae7, ac23, y25, n24, j23, a23, d23, d20, e18, a13, a16, k10, k11, k12, k13, k14, k15, k16, k17, l10, l11, l12, l13, l14, l15, l16, l17, m10, m11, m12, m13, m14, m15, m16, m17, n10, n11, n12, n13, n14, n15, n16, n17, p10, p11, p12, p13, p14, p15, p16, p17, r10, r11,r12, r13, r14, r15, r16, r17, t10, t11, t12, t13, t14, t15, t16, t17, u10, u11, u12, u13, u14, u15, u16, u17 1 should be tied to vddh via a 2k ? external pull-up resistor. 2 the default configuration of the cpm pins (pa[0?31], pb[4?31], pc[0?31], pd[4?31]) is input. to prevent excessive dc current, it is recommended to either pull unused pins to gnd or vddh, or to configure them as outputs. 3 must be pulled down or left floating. 4 if pci is not desired, must be pulled up or left floating. 5 sphere is not connected to die. 6 gndsyn (b18): this pin exists as a separate ground signal in mpc826x(a) devices; it does not exist as a separate ground signal on the mpc8275/MPC8270. new designs must connect b18 to gnd and follow the suggestions in section 4.6, ?layout practices .? old designs in which the mpc8275/MPC8270 is used as a drop-in replacement can leave the pin connected to gnd with the noise filtering capacitors. 7 xfc (a18) pin: this pin is used in mpc826x(a) devices; it is not used in mpc8275/MPC8270 because there is no need for external capacitor to operate the pll. new designs should connect a18 (xfc) pin to gnd. old designs in which the mpc8275/MPC8270 is used as a drop-in replacement can leave the pin connected to the current capacitor. table 22. mpc8275 and MPC8270 (vr and zq packages) pinout list (continued) pin name ball mpc8275/MPC8270 mpc8275 only
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 72 freescale semiconductor package description 9 package description the following sections provide the package parameters and mechanical dimensions. 9.1 package parameters package parameters are provided in ta ble 23 . table 23. package parameters package devices outline (mm) type interconnects pitch (mm) nominal unmounted height (mm) zu mpc8280 MPC8270 37.5 x 37.5 tbga 480 1.27 1.55 vr mpc8275vr MPC8270vr 27 x 27 pbga 516 1 2.25 zq mpc8275zq MPC8270zq 27 x 27 pbga 516 1 2.25
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 73 package description 9.2 mechanical dimensions figure 17 provides the mechanical dimensions and bottom surface nomenclature of the 480 tbga (zu) package. refer to table 2 . figure 17. mechanical dimensions and bottom surface nomenclature?480 tbga figure 18 provides the mechanical dimensions and bottom surface nomenclature of the 516 pbga (vr/zq) packages. dim millimeters min max a 1.45 1.65 a1 0.60 0.70 a2 0.85 0.95 a3 0.25 ? b 0.65 0.85 d 37.50 bsc d1 35.56 ref e 1.27 bsc e 37.50 bsc e1 35.56 ref notes: 1. dimensions and tolerancing per asme y14.5m-1994. 2. dimensions in millimeters. 3. dimension b is measured at the ildbllditlll
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 74 freescale semiconductor ordering information figure 18. mechanical dimensions and bottom surface nomenclature?516 pbga 10 ordering information figure 19 provides an example of the freescale part numbering nomenclature for the mpc8280. in addition to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s) in the part from the original production design. each part number also contains a revision code that refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. for more information, contact your local freescale sales office.
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 75 document revision history figure 19. freescale part number key 11 document revision history table 24. document revision history revision date substantive changes 0.1 ? initial public release 0.2 11/2002 table 22 , ?vr pinout?: addition of c18 to the ground (gnd) pin list (page 63) 0.3 6/2003 removal of notes stating ?no local bus? on vr-package devices. the MPC8270vr and the mpc8275vr have local bus support. references to ?g2 core? changed to ?g2_le core.? refer to the g2 core reference manual (g2corerm/d). addition of vccsyn to ?note? below ta b l e 4 , and to note 3 of ta b l e 5 figure 2 : new table 5 : addition of note 1 table 6 : addition of jb and jc . modifications to zu package values. table 7 : addition of various configurations, modification of values. addition of note 3. table 9 : addition of 66 mhz and 100 mhz values. addition of sp42a/sp43a. table 10 : addition of 66 mhz and 100 mhz values table 12 : sp30 values. sp33b @100 mhz value. removal of previous note 2. modification of current note 2. figure 5 , figure 6 , figure 7 , and figure 8 : addition of notes section 6.2: addition of note on pci timing table 15 , ta ble 1 6 , ta b l e 1 7 , ta b l e 1 8 , ta ble 1 9 : addition of note 1 concerning minimum operating frequencies addition of statement before clock tables about selection of clock configuration and input frequency table 20 and ta b l e 2 2 : addition of note 1 to cpm pins product code device number package processor frequency die revision level mpc 82xx c zu xxx (cpu/cpm/bus) x temperature range blank = 0 t a to 105 t j c = (-40) t a ? 105 t j zu = 480 tbga lead spheres vr = 516 pbga lead-free spheres zq = 516 pbga lead spheres
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 76 freescale semiconductor document revision history 1.0 2/2004 removal of ?advance information? and ?preliminary.? the mpc8280 is fully qualified. table 1 : new figure 1 : modification to note 2 section 1.1: core frequency range is 166?450 mhz addition of zq (516 pbga with lead spheres) package references table 4 : vdd and vccsyn modified to 1.45?1.60 v note following ta b l e 4 : modified table 5 : addition of note 2 regarding trst and poreset (see vih row of ta ble 5 ) table 5 : changed i ol for 60x signals to 6.0 ma table 5 : moved qreq to v ol : i ol = 3.2 ma table 5 : addition of critical interrupt (cint ) to irq5 for v ol (i ol = 6.0ma) table 6 : addition of jt and note 4 sections 4.1?4.5: new table 7 : modified power values (+ 150mw to each) table 8 : addition of note 2. changed pci impedance to 27 ?. table 9 : changes to sp36b, sp38a, sp38b, sp37a, sp39a, sp40 and sp41 table 10 : changes to sp16a, sp18a, sp20 and sp21 section 6.2: addition of note: clkin jitter and duty cycle table 11 : changes to sp13 @ 66 and 83 mhz, sp14 @ 83 mhz table 12 : change to sp30 (data bus signals). changes to sp33b. removal of note 2. table 15 through ta b l e 1 9 : modification of note 1 regarding cpu and cpm fmin. modification to corresponding values in tables. table 20 : addition of note 1 to trst (ah3) and poreset (ag6) table 20 : addition of rxd3 to cpm port pin pb14. previously omitted. table 20 : addition of critical interrupt (cint ) to b21 and u4. previously omitted. table 20 : addition of note 5 to ?no connect? (aa1, ag4) addition of ?note: temperature reflow for the vr package" on page 58 table 22 : addition of note 1 to trst (f22) and poreset (b25) table 22 : addition of previously omitted signals that are multiplexed with cpm port pins: pa6?fcc2_ut_rxaddr3 pa7?fcc2_ut_txaddr3 pa8?fcc2_ut_txaddr4 pb14?rxd3 pc19?spiclk pc22?fcc1_ut_txprty pc28?fcc2_ut_rxaddr4 table 22 : removal of serial interface 1 (si1) signals from port pins (see note 2 in figure 1 ): pa[6?9], pb[8?17, 20?25], pc[6?7, 10?13], pd[4, 10?13, 16, 23?28] table 22 : addition of critical interrupt (cint ) to ac1 and b14. previously omitted. table 22 : addition of note 5 to ?no connect? (e17, c23) table 24. document revision history revision date substantive changes
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 77 document revision history 1.2 12/2004 section 2: removed voltage tracking note table 3 : note 2 updated regarding vdd/vccsyn relationship to vddh during power-on reset table 5 : note 2 updated to reflect vih=2.5 for tck, trst, poreset; request for external pullup removed. table 5 : note 4 added regarding iic compatibility section 4.2: new information about jumper-to-case thermal resistance section 4.3: new information about jumper-to-board thermal resistance section 4.4: new information about estimation with simulation section 4.6: updated description of layout practices section 6: added sentence providing derating factor section 6.1, ?cpm ac characteristics ?: added note: rise/fall time on cpm input pins table 9 : updated values for following specs: sp42, sp43, sp42a table 10 : updated values for following specs: sp16b, sp18b, sp20, sp22 section 6.2: added spread sprectrum clocking note table 11 : combined specs sp11 and sp11a sections 7.2, 7.3: unit of ns added to tval notes section 7, ?clock configuration modes ?: updated all table footnotes reflect updated cpu fmin of 150 mhz commercial temp devices, 175 mhz extended temp; cpm fmin of 120 mhz. 1.3 01/2005 modification for correct display of assertion level (?overbar ?) for some signals table 24. document revision history revision date substantive changes
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 78 freescale semiconductor document revision history this page intentionally left blank
mpc8280 powerquicc ii? family hardware specifications, rev. 1.3 freescale semiconductor 79 document revision history this page intentionally left blank
mpc8280ec rev. 1.3 01/2005 freescale? and the freescale logo are trademarks of freescale semiconductor, inc. the powerpc name is a trademark of ibm corp. and is used under license. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2004. information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com email: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064, japan 0120 191014 +81 2666 8080 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate, tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 (800) 441-2447 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com

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